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https://github.com/mikecarper/MeshCore.git
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mikecarper
091c8d8324
Skip redundant modulation writes during owned fast RX retunes when the last acknowledged SF/BW/CR/LDRO tuple matches. Invalidate that cache after ordinary setters, failed writes, and lifecycle changes. Include the remaining scan, preamble, settling, and memory-soak experiments, their collectors, validation notes, and original capture records. Preserve capture bytes across checkouts and keep private soak credentials local. Run lab collector and compiled contract tests in CI. Update the expectation, profile mapping, and result-buffer tests for the extended lab tools, and make the private WiFi override header optional for ordinary soak diagnostics. Validation: 145 host tests passed from the staged source snapshot. Clean heltec_v4_repeater and Xiao_S3_WIO_companion_radio_usb builds passed their RAM/flash gates. All 229 staged capture files retain their original bytes; all 75 local documentation links resolve in the clean snapshot.
55 lines
2.2 KiB
C
55 lines
2.2 KiB
C
#pragma once
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// HIL only. Observe existing SPI reads/clears without changing their bytes.
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// Optional early IRQ polling is performed by the channel scheduler, not here.
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struct ChannelTraceEvent {
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uint32_t us, a, b;
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uint16_t irq;
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uint8_t channel, kind;
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};
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struct ChannelTrace {
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enum : uint8_t { Arm=1, Irq=2, Clear=3, Hop=4, Hold=5, Packet=6, Timeout=7, Frequency=8 };
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static constexpr unsigned Capacity=4096;
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ChannelTraceEvent events[Capacity];
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bool active=false, enabled=false;
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unsigned size=0, overflow=0;
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uint32_t origin=0, sequence=0, pollAt=0, pollCount=0, pollTotalUs=0, pollMaxUs=0;
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uint16_t irq=0;
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uint32_t rfWord=0, txWord=0, txCommandUs=0;
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uint32_t rfWrites=0, modulationWrites=0;
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uint32_t modulationWord=0;
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uint8_t channel=0;
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void add(uint8_t kind,uint32_t a=0,uint32_t b=0) {
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if(!active) return;
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if(size==Capacity) { ++overflow;return; }
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events[size++]={uint32_t(micros()-origin),a,b,irq,channel,kind};
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}
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void arm(uint32_t seq,uint8_t current,uint8_t expected,uint32_t visitAge) {
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size=overflow=0;origin=micros();sequence=seq;channel=current;irq=0;
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pollAt=origin;pollCount=pollTotalUs=pollMaxUs=0;active=enabled;
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add(Arm,expected,visitAge);
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}
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void observe(const uint8_t* out,size_t len,const uint8_t* in) {
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if(!out || !in) return;
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// Track actual command bytes even outside a capture, not just SW labels.
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if(len==5 && out[0]==0x86) {
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++rfWrites;
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rfWord=uint32_t(out[1])<<24 | uint32_t(out[2])<<16 | uint32_t(out[3])<<8 | out[4];
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add(Frequency,rfWord);
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}
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if(len==5 && out[0]==0x8b) {
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++modulationWrites;
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modulationWord=uint32_t(out[1])<<24 | uint32_t(out[2])<<16 | uint32_t(out[3])<<8 | out[4];
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}
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if(len==4 && out[0]==0x83) { txCommandUs=micros();txWord=rfWord; }
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if(!active) return;
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// Pinned SX126x Module: opcode, status dummy, two big-endian IRQ bytes.
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if(len==4 && out[0]==0x12) {
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const uint16_t value=uint16_t(in[2])<<8 | in[3];
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if(value!=irq) { irq=value;add(Irq); }
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} else if(len==3 && out[0]==0x02 && irq) {
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add(Clear,uint16_t(out[1])<<8 | out[2]);
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// Do not predict the clear's success: next actual read establishes it.
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}
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}
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} channelTrace;
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