mirror of
https://github.com/mikecarper/MeshCore.git
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mikecarper
091c8d8324
Skip redundant modulation writes during owned fast RX retunes when the last acknowledged SF/BW/CR/LDRO tuple matches. Invalidate that cache after ordinary setters, failed writes, and lifecycle changes. Include the remaining scan, preamble, settling, and memory-soak experiments, their collectors, validation notes, and original capture records. Preserve capture bytes across checkouts and keep private soak credentials local. Run lab collector and compiled contract tests in CI. Update the expectation, profile mapping, and result-buffer tests for the extended lab tools, and make the private WiFi override header optional for ordinary soak diagnostics. Validation: 145 host tests passed from the staged source snapshot. Clean heltec_v4_repeater and Xiao_S3_WIO_companion_radio_usb builds passed their RAM/flash gates. All 229 staged capture files retain their original bytes; all 75 local documentation links resolve in the clean snapshot.
93 lines
4.4 KiB
Python
93 lines
4.4 KiB
Python
"""HIL IRQ capture is bounded, observational and frozen before USB retrieval."""
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from pathlib import Path
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import unittest
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import test_sx1262_batched_modulation as compiler
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class ChannelTraceTests(unittest.TestCase):
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compile_run = compiler.BatchedModulationTests.compile_run
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def test_settle_is_additional_and_cycles_exclude_held_visits(self):
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source = (Path(__file__).resolve().parents[1] / "tools/hil/ProfileChannelVisitClock.h").read_text().replace("#pragma once", "")
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self.compile_run(r'''
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#include <cassert>
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@SOURCE@
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int main() {
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ChannelVisitClock v;
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v.begin(100,200,false);assert(v.dwell(500,100)==400); // zero-delay legacy clock
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v.begin(100,1100,true);assert(v.dwell(3711,100)==2611);
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assert(v.dwell(3712,100)==2612); // settling did not consume the 5.1-symbol visit
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assert(v.dwell(4100,4000)==100); // packet restart has no channel-settle delay
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v.begin(0xfffffff0u,0xfffffffau,true);assert(v.dwell(10,0xfffffff0u)==16);
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ChannelCycleClock c;uint32_t elapsed=0;
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assert(!c.hop(0,100,false,elapsed));
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for(unsigned ch=1;ch<4;++ch) assert(!c.hop(ch,100+ch*3000,false,elapsed));
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assert(c.hop(0,12100,false,elapsed) && elapsed==12000);
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assert(!c.hop(2,15000,true,elapsed));
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assert(!c.hop(0,25000,false,elapsed)); // a held visit invalidates this full cycle
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assert(c.hop(0,37000,false,elapsed) && elapsed==12000);
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}
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'''.replace("@SOURCE@", source))
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def test_held_occupancy_survives_receive_restart(self):
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source = (Path(__file__).resolve().parents[1] / "tools/hil/profile_switch_channels.h").read_text()
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self.assertIn("visitAge=now-channelSweep.visitStartedUs", source)
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self.assertIn("channelSweep.heldDwell.add(visitAge)", source)
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self.assertIn("channelTrace.add(ChannelTrace::Hop,visitAge", source)
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self.assertEqual(source.count("channelSweep.visitStartedUs=driver.receiveStartedUs();"), 2)
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def test_selected_sf_reaches_initial_hops_tx_and_cache_check(self):
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source = (Path(__file__).resolve().parents[1] / "tools/hil/profile_switch_channels.h").read_text()
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self.assertIn("p.sf=sf", source)
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for expected in ("sweepParams(0,preamble,sf,bwKhz)", "sweepParams(1,preamble,sf,bwKhz)",
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"setLoRaModulationParams(bwKhz,sf,5)", "channelSweep.sf=sf;",
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"channelSweep.bwKhz=bwKhz;", "p.bw=bwKhz",
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"chip.bandwidthKhz!=expectedParams.bw",
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"chip.spreadingFactor!=expectedParams.sf"):
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self.assertIn(expected, source)
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self.assertEqual(source.count("sweepParams(next,channelSweep.preamble,channelSweep.sf,channelSweep.bwKhz)"), 3)
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def test_passive_irq_decode_bounds_and_freeze(self):
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source = (Path(__file__).resolve().parents[1] / "tools/hil/ProfileChannelTrace.h").read_text().replace("#pragma once", "")
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harness = r'''
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#include <cassert>
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#include <cstdint>
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#include <cstddef>
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uint32_t clockUs=1000;
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uint32_t micros() { return clockUs; }
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@SOURCE@
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int main() {
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auto& t=channelTrace;
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t.arm(5,0,3,40);assert(t.size==0);
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t.enabled=true;t.arm(6,1,3,50);
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assert(t.size==1 && t.events[0].a==3 && t.events[0].b==50);
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uint8_t out[4]={0x12,0,0,0},in[4]={0,0,0,4};
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clockUs+=20;t.observe(out,4,in);
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assert(t.size==2 && t.events[1].irq==4 && t.events[1].us==20);
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t.observe(out,4,in);assert(t.size==2); // unchanged observations deduplicate
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uint8_t clear[3]={2,0,4};t.observe(clear,3,in);
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assert(t.events[2].kind==ChannelTrace::Clear && t.irq==4);
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in[3]=0;t.observe(out,4,in);assert(t.size==4 && t.irq==0);
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t.active=false;t.observe(out,4,in);t.add(ChannelTrace::Hop);assert(t.size==4);
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t.arm(7,2,0,0);
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for(unsigned i=0;i<ChannelTrace::Capacity+10;++i) t.add(ChannelTrace::Hop,i);
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assert(t.size==ChannelTrace::Capacity && t.overflow==11);
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t.arm(8,0,0,0);assert(t.size==1 && !t.overflow && t.sequence==8);
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t.active=false;
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uint8_t rf[5]={0x86,0x38,0xe0,0,0};t.observe(rf,5,in);
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assert(t.rfWord==0x38e00000);
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assert(t.rfWrites==1 && t.modulationWrites==0);
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uint8_t modulation[5]={0x8b,6,4,1,0};t.observe(modulation,5,in);
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assert(t.modulationWrites==1 && t.size==1);
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assert(t.modulationWord==0x06040100);
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uint8_t tx[4]={0x83,0,0,0};t.observe(tx,4,in);
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assert(t.txCommandUs==clockUs && t.txWord==t.rfWord && t.size==1);
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assert(out[0]==0x12 && clear[0]==2 && in[3]==0);
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}
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'''
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self.compile_run(harness.replace("@SOURCE@", source))
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if __name__ == "__main__":
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unittest.main()
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