mirror of
https://github.com/mikecarper/MeshCore.git
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mikecarper
091c8d8324
Skip redundant modulation writes during owned fast RX retunes when the last acknowledged SF/BW/CR/LDRO tuple matches. Invalidate that cache after ordinary setters, failed writes, and lifecycle changes. Include the remaining scan, preamble, settling, and memory-soak experiments, their collectors, validation notes, and original capture records. Preserve capture bytes across checkouts and keep private soak credentials local. Run lab collector and compiled contract tests in CI. Update the expectation, profile mapping, and result-buffer tests for the extended lab tools, and make the private WiFi override header optional for ordinary soak diagnostics. Validation: 145 host tests passed from the staged source snapshot. Clean heltec_v4_repeater and Xiao_S3_WIO_companion_radio_usb builds passed their RAM/flash gates. All 229 staged capture files retain their original bytes; all 75 local documentation links resolve in the clean snapshot.
76 lines
3.3 KiB
Python
76 lines
3.3 KiB
Python
"""Same-image RX-only one/two frequency-write ABBA timing; no RF TX."""
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import argparse
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import json
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from pathlib import Path
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import secrets
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import time
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from profile_switch import exchange
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from profile_switch_packets import open_port
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from profile_switch_dwell import reboot_boards
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from profile_switch_channels import channel_dwell_us
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def main():
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parser=argparse.ArgumentParser(description=__doc__)
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parser.add_argument('--port',required=True)
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parser.add_argument('--sf',type=int,choices=range(5,11),default=10)
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parser.add_argument('--output',type=Path,required=True)
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args=parser.parse_args()
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if args.output.exists():
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parser.error('fresh output required')
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result=dict(experiment='one_two_frequency_write_rx_only_abba',port=args.port,sf=args.sf,
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bw_khz=125,channels=4,preamble_symbols=32,dwell_symbols=5.1,
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settle_us=0,modulation_cache=True,expected_rx_gain_reg=0x94,
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seconds_per_trial=6,order=[False,True,True,False],complete=False,trials=[])
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seq=secrets.randbelow(0x3fffffff)
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port=None
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def save():
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args.output.write_text(json.dumps(result,indent=2)+'\n',encoding='utf-8')
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try:
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for repeated in result['order']:
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reboot_boards((args.port,))
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port=open_port(args.port)
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info=exchange(port,'info','bench',3)
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if info.get('frequency_repeat_ab')!=1 or info.get('rx_gain_reg')!=0x94:
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raise RuntimeError('Wrong HIL capability/gain')
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if exchange(port,f'scanfreqrepeat {int(repeated)}','frequency_repeat',2)['frequency_repeat']!=repeated:
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raise RuntimeError('Frequency policy mismatch')
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if not exchange(port,'scanmodcache 1','modulation_cache',2)['modulation_cache']:
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raise RuntimeError('Cache policy mismatch')
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dwell=channel_dwell_us(args.sf,5.1)
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seq+=1
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config=exchange(port,f'scanstart 4 32 {seq} {dwell} 0 {args.sf} 125','listening',3,seq,cached=True)
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time.sleep(6)
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seq+=1
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status=exchange(port,f'scanstatus {seq}','result',3,seq,cached=True)
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result['trials'].append(dict(repeated=repeated,info=info,config=config,status=status))
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save()
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n=status['switch']['n']
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if n<64 or any(status[k] for k in ('failures','rx_mode_errors','cache_errors')):
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raise RuntimeError('Insufficient hops or hardware/configuration error')
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if (status['frequency_repeat']!=repeated or status['rx_gain_reg']!=0x94
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or status['rf_commands']!=n*(2 if repeated else 1)
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or status['settle_us']!=0 or status['modulation_commands']!=0):
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raise RuntimeError('Measured command/gain/delay policy mismatch')
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print(f"repeat={repeated}: {n} hops, mean {status['switch']['mean_us']:.3f} us, "
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f"0x86={status['rf_commands']}, 0x8B={status['modulation_commands']}",flush=True)
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exchange(port,'scanstop','stopped',2)
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port.close();port=None
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result['complete']=True
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except Exception as error:
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result['error']=str(error)
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raise
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finally:
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if port:
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port.close()
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try:
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reboot_boards((args.port,))
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except Exception as error:
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result['cleanup_error']=str(error)
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save()
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if __name__=='__main__':
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main()
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