mirror of
https://github.com/mikecarper/MeshCore.git
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mikecarper
091c8d8324
Skip redundant modulation writes during owned fast RX retunes when the last acknowledged SF/BW/CR/LDRO tuple matches. Invalidate that cache after ordinary setters, failed writes, and lifecycle changes. Include the remaining scan, preamble, settling, and memory-soak experiments, their collectors, validation notes, and original capture records. Preserve capture bytes across checkouts and keep private soak credentials local. Run lab collector and compiled contract tests in CI. Update the expectation, profile mapping, and result-buffer tests for the extended lab tools, and make the private WiFi override header optional for ordinary soak diagnostics. Validation: 145 host tests passed from the staged source snapshot. Clean heltec_v4_repeater and Xiao_S3_WIO_companion_radio_usb builds passed their RAM/flash gates. All 229 staged capture files retain their original bytes; all 75 local documentation links resolve in the clean snapshot.
55 lines
3.0 KiB
Python
55 lines
3.0 KiB
Python
import unittest
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from profile_switch_rollback import settling_budget, check_timing, CASES, PREAMBLE_US, DWELL_US
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class RollbackTests(unittest.TestCase):
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def test_full_retune_repeat_requires_two_real_passes(self):
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case=dict(rollback=0,cache=False,repeat=True,retune_passes=2)
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status=dict(switch=dict(n=100),failures=0,rx_mode_errors=0,cache_errors=0,rx_errors=0,
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rollback=0,rx_gain_reg=148,settle_us=0,frequency_repeat=True,
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optimized_rx_resumes=200,rf_commands=400,modulation_commands=200,
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warm_standby=True,batched_modulation=True,bulk_spi=True,retune_passes=2,
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first_pass=dict(n=100),second_pass=dict(n=100),second_pass_blocked=0)
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check_timing(status,case,0)
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detour_case=dict(case,first_pass_detour=True)
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detour_status=dict(status,first_pass_detour=True,detour=dict(n=100,bad=0))
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check_timing(detour_status,detour_case,0)
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for detail in (dict(n=99,bad=0),dict(n=100,bad=1)):
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with self.assertRaises(RuntimeError):
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check_timing(dict(detour_status,detour=detail),detour_case,0)
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for key,value in (('rf_commands',200),('modulation_commands',100),
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('optimized_rx_resumes',100),('second_pass',dict(n=0)),
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('second_pass_blocked',1),('retune_passes',1)):
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with self.assertRaises(RuntimeError): check_timing(dict(status,**{key:value}),case,0)
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def test_maximum_delay_retains_measured_switch_and_reserve(self):
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for switch in (800, 1200, 8000):
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delay = settling_budget(switch)
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self.assertEqual(delay % 100, 0)
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self.assertLessEqual(4*(DWELL_US+switch+delay+500), PREAMBLE_US)
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self.assertGreater(4*(DWELL_US+switch+delay+600), PREAMBLE_US)
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with self.assertRaises(RuntimeError):
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settling_budget(24000)
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def test_observed_commands_must_match_each_rollback(self):
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for case in CASES:
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bits = case['rollback']
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fast = bits & 9 == 0
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mods = 3 if bits & 2 else 0 if fast and case['cache'] else 1
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status = dict(switch=dict(n=100), failures=0, rx_mode_errors=0, cache_errors=0,
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rx_errors=0, rollback=bits, rx_gain_reg=148, settle_us=0,
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frequency_repeat=case['repeat'], optimized_rx_resumes=int(fast)*100,
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rf_commands=100*(2 if case['repeat'] else 1), modulation_commands=100*mods,
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warm_standby=bits & 8 == 0, batched_modulation=bits & 2 == 0,
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bulk_spi=bits & 4 == 0)
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status['tcxo_us']=case.get('tcxo_us',1600)
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check_timing(status, case, 0)
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with self.assertRaises(RuntimeError):
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check_timing(dict(status, modulation_commands=-1), case, 0)
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with self.assertRaises(RuntimeError):
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check_timing(dict(status, rf_commands=-1), case, 0)
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if __name__ == '__main__':
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unittest.main()
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