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Double center-frequency write: V4 transmitter / XIAO receiver
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Double center-frequency write: V4 transmitter / XIAO receiver
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Classic ESP32 image memory budget
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ESP-NOW bridge: simple setup
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Four fixed transmitters: longer dwell repeats
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Four fixed transmitters / fast single-pass receiver
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Full Companion: turn features on and off
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Companion USB CLI and binary switcher
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Full USB logging repair — 1.17.1.6
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GPS Tracking
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Halo and Keymind Branch Settings
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XIAO Bluetooth stealth hardware validation - 2026-09-07
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Hardware validation checklist
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LoRa CLI Host Service
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MeshCore KISS Modem Protocol
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Scripted LoRa OTA from start to finish
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Shrinking the per-connection TLS footprint on non-PSRAM observers
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Mixed-bandwidth two-channel reception test
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Equal-symbol-time mixed SF/BW, four-channel test
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ESP32-S3 NimBLE Full Companion trial
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ESP32-S3 NimBLE trial results, 2026-09-08
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nRF52 USB READY hang
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nRF52 Companion automatic ExtraFS recovery
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nRF52 Power Management
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Number Allocations
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Easy firmware updates over LoRa
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MeshTower V2 microSD LoRa OTA
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nRF52 bootloader updates over LoRa
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nRF52 repeater LoRa OTA with external QSPI
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MeshCore OTA - .mota container &amp; LoRa protocol
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Updating your node over the air (OTA) - user guide
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Packet Format
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<h1 id="double-center-frequency-write-v4-transmitter-xiao-receiver">Double center-frequency write: V4 transmitter / XIAO receiver</h1>
<p>2026-09-14. <strong>Completed bounded comparison: neither single nor duplicate
frequency writes reached 400/400. The duplicate adds about 86 us per hop.</strong>
No production default was changed. Both radios are idle with HIL installed;
the duplicate-write toggle is off. The earlier descending-SF sweep and its
follow-up remain paused; no new exhaustive settling sweep was launched.</p>
<h2 id="hardware-and-control">Hardware and control</h2>
<ul>
<li>RX: XIAO ESP32-S3/WIO SX1262, COM31, MAC 28:84:85:b4:09:80. Normal gain
register 0x94, unchanged-modulation cache enabled, buffered 8 MHz SPI.</li>
<li>TX: newly connected Heltec V4, COM7, MAC 44:1b:f6:6a:e8:44. Hardware probe
found ESP32-S3, 2 MB embedded PSRAM and 16 MB flash. HIL detected KCT8103L
FEM and reported the amplified TX path; chip RX gain 0x96.</li>
<li>User explicitly authorized erasing the V4 without backup. Its full flash
was erased and a verified HIL upload completed. XIAO's previous HIL image
was replaced with a verified same-image A/B-capable build. No private
backup contents were read; RAK and other boards were not touched.</li>
<li>SF10/125 kHz, CR4/5, four centers 909.500/909.750/910.000/910.250 MHz,
5.1-symbol visits (41,780 us), 32-symbol TX preamble, zero added settling,
synthetic 16-byte packets, -9 dBm <strong>chip request</strong>. No extra IRQ polling.</li>
</ul>
<p>The V4 FEM uses the repository's production detection and TX/RX control.
HIL restores RX after success or error on each direct transmit path. The
GC1109 branch (not detected here) uses bypass according to
<a href="https://resource.heltec.cn/download/WiFi_LoRa_32_V4/datasheet/GC1109_EN_V0.9.2.pdf">GC1109 table 4</a>.
The detected KCT8103L uses its amplified path; antenna-port TX power was not
measured. This is not a power-matched Indicator/V4 comparison.</p>
<h2 id="exact-experiment">Exact experiment</h2>
<p><code>scanfreqrepeat 1</code> makes the HIL <code>ExperimentalSX1262</code> repeat the same
SetRfFrequency (0x86) immediately after the first successful frequency call,
before modulation, packet parameters and RX restart. The second call skips
the image-calibration check, but keeps normal BUSY/status handling. Only an
identified RX-to-RX hop may repeat; ordinary setup/TX does not. Either write's
failure propagates through the existing failed profile-apply path. The toggle
defaults off at reboot and cannot change during an active scan.</p>
<p>Both modes use the same XIAO binary. Actual SPI command counts, not only
software policy labels, are checked against one or two 0x86 writes per hop.
The modulation cache remains on in both modes.</p>
<h2 id="rx-only-timing">RX-only timing</h2>
<p>Six-second windows in single/double/double/single order, with reboot/clean
setup between windows. No reference packets transmitted during this phase.</p>
<table>
<thead>
<tr>
<th>Frequency writes</th>
<th style="text-align: right;">Hops</th>
<th style="text-align: right;">Mean switch</th>
<th style="text-align: right;">Actual 0x86</th>
<th style="text-align: right;">Actual 0x8B</th>
</tr>
</thead>
<tbody>
<tr>
<td>Single, first</td>
<td style="text-align: right;">142</td>
<td style="text-align: right;">451.965 us</td>
<td style="text-align: right;">142</td>
<td style="text-align: right;">0</td>
</tr>
<tr>
<td>Double, first</td>
<td style="text-align: right;">141</td>
<td style="text-align: right;">538.213 us</td>
<td style="text-align: right;">282</td>
<td style="text-align: right;">0</td>
</tr>
<tr>
<td>Double, second</td>
<td style="text-align: right;">141</td>
<td style="text-align: right;">538.170 us</td>
<td style="text-align: right;">282</td>
<td style="text-align: right;">0</td>
</tr>
<tr>
<td>Single, second</td>
<td style="text-align: right;">142</td>
<td style="text-align: right;">451.930 us</td>
<td style="text-align: right;">142</td>
<td style="text-align: right;">0</td>
</tr>
</tbody>
</table>
<p>Weighted means: <strong>451.948 us single, 538.192 us double</strong>: +86.244 us / +19.1%.
All 566 hops had zero retune, RX-mode and cache errors. Maximum observed
switch costs were 594 us single and 674 us double; these are samples, not
hard latency guarantees. Unheld full-cycle means were about 168.942 ms versus
169.285 ms.</p>
<h2 id="packet-checks">Packet checks</h2>
<p>Single first, then double, each up to 100 packets/channel and stopping on its
first miss; a 400/400 result would have stopped all RF testing. Neither passed.</p>
<table>
<thead>
<tr>
<th>Frequency writes</th>
<th style="text-align: right;">Valid before first miss</th>
<th style="text-align: right;">Failed packet</th>
<th style="text-align: right;">RF-run mean switch</th>
<th style="text-align: right;">Hops / 0x86 writes</th>
</tr>
</thead>
<tbody>
<tr>
<td>Single</td>
<td style="text-align: right;">1</td>
<td style="text-align: right;">2, channel 2</td>
<td style="text-align: right;">452.719 us</td>
<td style="text-align: right;">235 / 235</td>
</tr>
<tr>
<td>Double</td>
<td style="text-align: right;">4</td>
<td style="text-align: right;">5, channel 2</td>
<td style="text-align: right;">542.063 us</td>
<td style="text-align: right;">255 / 510</td>
</tr>
</tbody>
</table>
<p>Both failed packets were receiver timeouts, with TX success acknowledged,
zero device-error flags and RX mode still active. Both settings reported zero
retune, RX-mode, cache and RX errors. Ordinary processing after received
packets caused one/four modulation rewrites respectively; pure RX-only timing
above is the cleaner comparison of the duplicate cost.</p>
<p>All five good V4 packets reported <strong>-19 dBm RSSI</strong>. SNR was +9.0 dB in the
single-write sample and +8.2..+9.2 dB (mean +8.675 dB) for four double-write
samples. The previous Indicator run had 547 good packets at average -40.547
dBm RSSI, +8.311 dB SNR. Thus this V4 setup was about 21.5 dB stronger as seen
by the receiver. Hardware/antenna/placement/power differences remain
confounded; neither the Indicator nor close-range effects are proven causes.</p>
<p>One versus four successes before a miss is too small and stop-conditioned to
establish a reliability improvement or packet-error rate. Repeating center
frequency did not remove the observed failure at this setting. No results for
lower SFs or added settling delays are claimed for the V4. A weaker received
signal is needed before treating a transmitter swap as a clean comparison.</p>
<h2 id="artifacts-and-checks">Artifacts and checks</h2>
<p>Base checkout <code>0e5955f889788a4317863e731b38ffe09e3d5441</code>, branch
<code>keymindCascade</code>, plus local uncommitted changes. RadioLib 7.7.1 pinned at
<code>187ef24791c3d844939b2be13a68bd890bd04e4c</code>, Espressif32 6.11.0 / Arduino
ESP32 2.0.17. Both builds/uploads succeeded and uploader verified written
data. The 59 selected host/native tests passed (39 collectors, ten profile,
four SX1262, five radio and one receive-mode), including FEM restore on error
and frequency-repeat scope/error propagation. Temporary build overlay removed.</p>
<p>Actually loaded firmware SHA-256:</p>
<ul>
<li>XIAO: <code>9f82d86ea78cfa6bc03fef4925f10c918c8b9fc7a96a7d2b565a04bd2f281288</code></li>
<li>V4: <code>2ea2ce37d9d66fb4f8ec9cf3cedfbe7d4eb6d08bfe9abe6c817e5afb04885636</code></li>
</ul>
<p>Raw evidence and byte-preserving SHA-256:</p>
<ul>
<li><a href="../tools/hil/profile_switch_frequency_sf10_rx_only_results.json">RX-only ABBA</a>:
<code>38ded968a60ff19f45618ec35d75ce46354d81f163879185e9d6ff0e68da3ae0</code></li>
<li><a href="../tools/hil/profile_switch_frequency_v4_sf10_off_results.json">Single-write packets</a>:
<code>4cadeba0d22b3ec6158ff295f1becfb57fde7ef8bf7fabbdbc6295f274619557</code></li>
<li><a href="../tools/hil/profile_switch_frequency_v4_sf10_on_results.json">Double-write packets</a>:
<code>46bea8d9c095847ef8ccf4a4ed51ab5404eb5bb87d9cf62b832c3298159d1525</code></li>
</ul>
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