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PR #7 review and validation
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<h1 id="sf10125-rollback-and-wider-spacing-failure-isolation">SF10/125 rollback and wider-spacing failure isolation</h1>
<p>2026-09-14. <strong>No strict four-channel 400/400 pass. Reverting the switching
optimizations did not remove failures. Off-channel reception also occurs with
a fixed, fully initialized receiver, without any channel switching.</strong> A traced
timeout shows an off-channel preamble holding the scanner away from the
intended channel until after its transmit preamble. Wider spacing did not
eliminate either wrong-channel delivery or actual missing packets.</p>
<p>This isolates a concrete scanner failure mechanism, not the underlying
physical RF cause. Commanded frequency words are observed, but actual emitted
spectrum, antenna-port power, image responses and overload have not been
independently measured. Do not claim front-end saturation or a specific spur
as proven. Do not treat these first-failure-censored samples as unbiased PER.</p>
<h2 id="fixture-and-requested-controls">Fixture and requested controls</h2>
<ul>
<li>RX: XIAO ESP32-S3 / Wio SX1262, COM31, MAC 28:84:85:B4:09:80; normal RX gain
register 0x94 throughout (boosted gain off).</li>
<li>TX: XIAO nRF52840 / Wio SX1262, COM15, serial B35E71C1C3726CE7.</li>
<li>SF10, 125 kHz BW, CR4/5, 32-symbol preamble, 16-byte sequenced CHS1 probes,
-9 dBm chip request, four channels, 5.1-symbol post-settle listening visits.</li>
<li>Original centers: 909.5, 909.75, 910.0, 910.25 MHz. User-requested wider
centers: 909.5, 910.5, 911.5, 912.5 MHz (1 MHz spacing).</li>
<li>Existing fixed-channel positive control was 100/100; see
<code>sf10_nrf52_double_write_settling_validation.md</code>. No failed packets retried.</li>
<li>Unrelated RAK COM29 was not opened. New nRF52 upload was application-only,
using normal SoftDevice ID 0x0123 validation; no bootloader/SoftDevice erase.</li>
</ul>
<p>Rollback modes are runtime HIL controls on the same current source, not
historical firmware checkouts. No production default or receive safety guard
was changed during this investigation. Tests preserve ownership, packet-in-
progress, BUSY and command-result checks. Existing unrelated working-tree
changes were left intact. No commit or push was requested this turn.</p>
<h2 id="maximum-practical-settling-control">Maximum practical settling control</h2>
<p>At SF10/125, a symbol is 8,192 us, the programmed preamble is 262,144 us,
and each 5.1-symbol post-settle visit is 41,780 us. For each rollback mode:</p>
<ol>
<li>Measure six seconds of RX-only switching without added delay.</li>
<li>Choose the largest 100 us delay step satisfying
<code>4 * (41780 + observed_max_switch_us + added_delay_us + 500) &lt;= 262144</code>.</li>
<li>Measure another six seconds; require at least eight full idle cycles and
maximum observed idle cycle below the preamble before allowing TX.</li>
</ol>
<p>The 500 us per-hop reserve covers some observed scheduling variation, not
all possible jitter. RX is active during added settling. Near-ceiling cycle
timing is not itself a guarantee of acquisition for every arrival phase,
especially when an IRQ causes an extended packet hold. Idle-cycle statistics
exclude guard/packet-held visits; those are measured separately.</p>
<h2 id="250-khz-spacing-eleven-rollback-cases">250 kHz spacing: eleven rollback cases</h2>
<p>Each case stopped on its <strong>first probe</strong>, TX channel 3, with a real timeout.
No strict 400/400 pass, TX fault, RX mode/cache failure, or hardware error.
The first nine cases used the checkout's existing 1,600 us TCXO setting;
the final two explicitly restored 6,000 us. Production timing was not edited.</p>
<table>
<thead>
<tr>
<th>Case</th>
<th style="text-align: right;">Added delay (us)</th>
<th style="text-align: right;">Zero-delay mean switch (us)</th>
<th style="text-align: right;">Max settled idle cycle (us)</th>
</tr>
</thead>
<tbody>
<tr>
<td>Fast, cached modulation, double frequency write</td>
<td style="text-align: right;">22500</td>
<td style="text-align: right;">535.88</td>
<td style="text-align: right;">259297</td>
</tr>
<tr>
<td>Always write modulation</td>
<td style="text-align: right;">22500</td>
<td style="text-align: right;">625.50</td>
<td style="text-align: right;">259682</td>
</tr>
<tr>
<td>Individual SF/BW/CR writes</td>
<td style="text-align: right;">22200</td>
<td style="text-align: right;">840.97</td>
<td style="text-align: right;">259346</td>
</tr>
<tr>
<td>Full normal RX restart</td>
<td style="text-align: right;">22200</td>
<td style="text-align: right;">896.89</td>
<td style="text-align: right;">259577</td>
</tr>
<tr>
<td>Full RX + individual modulation</td>
<td style="text-align: right;">22000</td>
<td style="text-align: right;">1113.95</td>
<td style="text-align: right;">259623</td>
</tr>
<tr>
<td>Above + byte-wise SPI, warm XOSC</td>
<td style="text-align: right;">21800</td>
<td style="text-align: right;">1215.79</td>
<td style="text-align: right;">259220</td>
</tr>
<tr>
<td>Above + RC standby, 1.6 ms TCXO</td>
<td style="text-align: right;">20100</td>
<td style="text-align: right;">2942.50</td>
<td style="text-align: right;">259339</td>
</tr>
<tr>
<td>Fast, cached modulation, single frequency write</td>
<td style="text-align: right;">22600</td>
<td style="text-align: right;">450.25</td>
<td style="text-align: right;">259341</td>
</tr>
<tr>
<td>RC/full RX/individual/byte-wise, single write, 1.6 ms TCXO</td>
<td style="text-align: right;">20200</td>
<td style="text-align: right;">2837.50</td>
<td style="text-align: right;">259329</td>
</tr>
<tr>
<td>RC/full RX/individual/byte-wise, double write, 6 ms TCXO</td>
<td style="text-align: right;">15800</td>
<td style="text-align: right;">7293.25</td>
<td style="text-align: right;">259550</td>
</tr>
<tr>
<td>RC/full RX/individual/byte-wise, single write, 6 ms TCXO</td>
<td style="text-align: right;">15800</td>
<td style="text-align: right;">7190.31</td>
<td style="text-align: right;">259139</td>
</tr>
</tbody>
</table>
<p>Actual frequency/modulation command counts and fast-RX counts verified each
policy. Slower modes received less added delay to preserve the total sweep
budget. These are eleven probes with eleven timeouts, <strong>not eleven complete
400-packet runs</strong>. Packet arrival pauses use the same seeded scheduling
method but not hardware-synchronized identical RF phases across modes.</p>
<h2 id="fixed-frequency-controls-off-channel-responses-without-switching">Fixed-frequency controls: off-channel responses without switching</h2>
<p>Each pair received three independent probes after full normal initialization.
Positive controls were interleaved. The receiver remained at one frequency:
zero observed frequency commands after setup, no hopping or cache shortcut.
Payload success requires the exact expected sequence/channel/body, length 16
and clean CRC. It does not require RX center to equal TX center in this
explicit offset diagnostic. Offset below means programmed RX minus TX.</p>
<table>
<thead>
<tr>
<th>Spacing</th>
<th style="text-align: right;">RX-TX offset (kHz)</th>
<th style="text-align: right;">Probes</th>
<th style="text-align: right;">Intact expected payloads</th>
<th style="text-align: right;">Preamble IRQ seen</th>
</tr>
</thead>
<tbody>
<tr>
<td>250 kHz</td>
<td style="text-align: right;">0</td>
<td style="text-align: right;">6</td>
<td style="text-align: right;">6</td>
<td style="text-align: right;">6</td>
</tr>
<tr>
<td>250 kHz</td>
<td style="text-align: right;">-250</td>
<td style="text-align: right;">3</td>
<td style="text-align: right;">2</td>
<td style="text-align: right;">3</td>
</tr>
<tr>
<td>250 kHz</td>
<td style="text-align: right;">-500</td>
<td style="text-align: right;">3</td>
<td style="text-align: right;">0</td>
<td style="text-align: right;">3</td>
</tr>
<tr>
<td>250 kHz</td>
<td style="text-align: right;">-750</td>
<td style="text-align: right;">3</td>
<td style="text-align: right;">0</td>
<td style="text-align: right;">3</td>
</tr>
<tr>
<td>250 kHz</td>
<td style="text-align: right;">+250</td>
<td style="text-align: right;">3</td>
<td style="text-align: right;">0</td>
<td style="text-align: right;">2</td>
</tr>
<tr>
<td>1 MHz</td>
<td style="text-align: right;">0</td>
<td style="text-align: right;">6</td>
<td style="text-align: right;">6</td>
<td style="text-align: right;">6</td>
</tr>
<tr>
<td>1 MHz</td>
<td style="text-align: right;">-1000</td>
<td style="text-align: right;">3</td>
<td style="text-align: right;">2</td>
<td style="text-align: right;">3</td>
</tr>
<tr>
<td>1 MHz</td>
<td style="text-align: right;">-2000</td>
<td style="text-align: right;">3</td>
<td style="text-align: right;">0</td>
<td style="text-align: right;">0</td>
</tr>
<tr>
<td>1 MHz</td>
<td style="text-align: right;">-3000</td>
<td style="text-align: right;">3</td>
<td style="text-align: right;">3</td>
<td style="text-align: right;">3</td>
</tr>
<tr>
<td>1 MHz</td>
<td style="text-align: right;">+1000</td>
<td style="text-align: right;">3</td>
<td style="text-align: right;">3</td>
<td style="text-align: right;">3</td>
</tr>
</tbody>
</table>
<p>At 250 kHz spacing, the two valid -250 kHz-offset packets reported RSSI
-91/-90 dBm and SNR -12.8/-10.8 dB. At 1 MHz spacing, valid off-channel
packets reported RSSI -102..-109 dBm and SNR -11.5..-15.8 dB. Wider on-channel
controls were all -33 dBm, SNR +8.0..+8.8 dB. These are radio-reported values,
not calibrated measurements of transmitted spurs or receiver rejection.</p>
<p>The non-monotonic offset pattern means that increasing spacing alone cannot
be assumed to remove this response. These fixed-frequency tests rule out a
channel-hop shortcut as a necessary condition for the observed off-channel
packets; they do not establish which physical component produces them.</p>
<h2 id="a-traced-real-timeout-at-250-khz-spacing">A traced real timeout at 250 kHz spacing</h2>
<p>Fast/double-write RX, +22,500 us settling. One channel-3 probe timed out with
TX rc=0, RX mode=1 and device errors=0. The trace contains 454 events, overflow
0. Trace adds 64 us IRQ polling; use it for ordering, not an unperturbed timing
A/B comparison. Times below are relative to receiver expectation arming.</p>
<table>
<thead>
<tr>
<th style="text-align: right;">RX time (ms)</th>
<th>Evidence</th>
</tr>
</thead>
<tbody>
<tr>
<td style="text-align: right;">169.190</td>
<td>Frequency command for channel 3, 910.25 MHz</td>
</tr>
<tr>
<td style="text-align: right;">234.032</td>
<td>Leaves channel 3 for channel 0</td>
</tr>
<tr>
<td style="text-align: right;">298.869</td>
<td>Frequency command for channel 1, 909.75 MHz</td>
</tr>
<tr>
<td style="text-align: right;">330.030</td>
<td>PREAMBLE_DETECTED (0x0004) while on channel 1</td>
</tr>
<tr>
<td style="text-align: right;">363.632</td>
<td>Requested next hop is held by receive-in-progress guard</td>
</tr>
<tr>
<td style="text-align: right;">726.734</td>
<td>Guard clears the lingering preamble IRQ</td>
</tr>
<tr>
<td style="text-align: right;">726.826</td>
<td>Frequency command for channel 2</td>
</tr>
<tr>
<td style="text-align: right;">791.654</td>
<td>Finally commands intended channel 3 again</td>
</tr>
<tr>
<td style="text-align: right;">814.586</td>
<td>Channel-3 hop/settling completes</td>
</tr>
</tbody>
</table>
<p>TX setup was 86,914 us and its transmit call 529,297 us. Host/firmware timing
places TX RF start approximately 287..289 ms after RX arming and the end of
its programmed preamble around 550 ms. This estimate is not a synchronized
RF measurement, but the receiver's several-hundred-millisecond absence from
the intended channel is much larger than USB timestamp uncertainty.</p>
<p>The held channel-1 visit measured <strong>427,395 us</strong>, versus normal idle four-
channel cycle maximum <strong>259,358 us</strong>. The guard timeout is consistent with
<code>RadioLibWrapper::calcMaxPacketMillis</code>: <code>(32 + 8 + 4.25) * 8192 = 362496 us</code>,
rounded to 363 ms. <code>CustomSX1262::isReceiving()</code> starts that timer when the
guard first observes the preamble, here later than the diagnostic IRQ poll.</p>
<p>Thus an off-channel preamble can monopolize the scanner long enough to miss
the real channel. Do not simply remove or shorten this safety guard as a
production fix: it also protects legitimate weak or long-preamble reception.</p>
<h2 id="1-mhz-spacing-strict-results-versus-payload-delivery">1 MHz spacing: strict results versus payload delivery</h2>
<p>Three strict rollback cases (fast double, fast single, fully rolled back
single/6 ms) each stopped at their first probe. All three actually decoded
the intact channel-3 payload while programmed for channel 2: RX 911.5 MHz,
TX 912.5 MHz, RF word at read 955777024. They are <strong>channel mismatches, not
lost payloads</strong>. RSSI was -102/-101/-101 dBm; SNR -11.5/-11.5/-11.2 dB.</p>
<p>An explicitly separate payload-delivery diagnostic then continued through
such packets while retaining strict validity in raw evidence:</p>
<table>
<thead>
<tr>
<th>Mode</th>
<th style="text-align: right;">Added delay</th>
<th style="text-align: right;">Delivered before stop</th>
<th style="text-align: right;">Strict same-channel</th>
<th>Stop</th>
<th style="text-align: right;">Mean switch</th>
<th style="text-align: right;">Max idle cycle</th>
</tr>
</thead>
<tbody>
<tr>
<td>Fast, cached, double write</td>
<td style="text-align: right;">22.5 ms</td>
<td style="text-align: right;">3 of 4 probes</td>
<td style="text-align: right;">0</td>
<td>TX channel 0 timed out</td>
<td style="text-align: right;">557.721 us</td>
<td style="text-align: right;">259381 us</td>
</tr>
<tr>
<td>RC/full RX/individual/byte-wise, single write, 6 ms TCXO</td>
<td style="text-align: right;">15.8 ms</td>
<td style="text-align: right;">2 of 3 probes</td>
<td style="text-align: right;">0</td>
<td>TX channel 1 timed out</td>
<td style="text-align: right;">7310.510 us</td>
<td style="text-align: right;">259643 us</td>
</tr>
</tbody>
</table>
<p>Every delivered packet in these two runs arrived one programmed channel below
its transmitter. Both runs had zero mode/cache/RX/device errors and actual
switch-policy counts matched. Neither is a 400/400 pass, even under the relaxed
delivery-only criterion. The true timeout in the fully rolled-back path also
shows the problem is not limited to the accelerated RX restart or 0x8B cache.
No traces were enabled for these two runs, so do not assign their individual
timeouts the exact IRQ timeline from the earlier traced probe.</p>
<h2 id="changes-and-verification">Changes and verification</h2>
<ul>
<li>HIL-only rollback, explicit TCXO timing, selectable 250/1000 kHz spacing,
frequency-command trace events and fixed-frequency offset controls.</li>
<li>Separate opt-in payload-delivery test; strict wire validity remains intact.
Host/device counters distinguish strict from off-channel deliveries;
settling sweeps reject delivery-only captures, including reused evidence.</li>
<li>16 native profile tests and 46 HIL host tests passed. Receiver and nRF52
builds/uploads succeeded with normal verification. Receiver reported
94,844 bytes RAM / 366,777 bytes flash; nRF52 18,220 / 95,572 bytes.</li>
<li><code>git diff --check</code> passed; unrelated pre-existing CRLF warnings only.</li>
<li>Temporary PlatformIO overlay removed. Controllers stopped, both boards
rebooted idle with HIL firmware retained. No autonomous TX or restoration.</li>
</ul>
<p>Next useful isolation is the physical off-channel response (controlled RF
attenuation or reversed radio roles), followed by safe acquisition/hold-policy
experiments. More settling delay alone does not address the demonstrated
false-hold mechanism. No claim of an identified silicon defect or verified
production fix is made here.</p>
<h2 id="evidence-provenance-sha-256">Evidence provenance (SHA-256)</h2>
<p>Raw JSON files below are under <code>tools/hil/</code>; prior captures were not rewritten.
Matrix manifests include per-case paths and timing controls. All listed new
experiments completed under their stated stopping policies without fixture or
cleanup errors. Completed first-failure runs still have incomplete 400-packet
levels by design.</p>
<table>
<thead>
<tr>
<th>Capture</th>
<th>SHA-256</th>
</tr>
</thead>
<tbody>
<tr>
<td>profile_switch_sf10_rollback_results.json</td>
<td><code>e87c504b3c89fbafe90c18fcd0ab37df34a6aeb51d95b5c69f58d60f70de185a</code></td>
</tr>
<tr>
<td>profile_stationary_sf10_offset_results.json</td>
<td><code>d3d87315513a70fc3f00cc7f17369043328f53ee3028d499087b21e767370ab7</code></td>
</tr>
<tr>
<td>profile_switch_sf10_rollback_fast_trace_results.json</td>
<td><code>8ac9db50f0f06eb7511d7d233957119618df62afdc7112dd83eb68d292fcd725</code></td>
</tr>
<tr>
<td>profile_switch_sf10_rollback_6ms_results.json</td>
<td><code>74e7bfeb23bc569a5786e2322b5e3b1753cba9f628e2969bf4f5c4296ca5817a</code></td>
</tr>
<tr>
<td>profile_switch_sf10_wide_rollback_results.json</td>
<td><code>d79096fbe3e15e0375457b487fd40be3418789e798a978efb79d8298c880eea2</code></td>
</tr>
<tr>
<td>profile_switch_sf10_wide_payload_results.json</td>
<td><code>1316a2c2f32a8c0773fc56587c4220ee8f6f6cdf4ab9b87e00fd361fc9395257</code></td>
</tr>
<tr>
<td>profile_switch_sf10_wide_legacy_payload_results.json</td>
<td><code>fcf2123270634e2f27800787e20b9b8b7ae63bcfb03e17d26a4a4f6f4e23d32f</code></td>
</tr>
<tr>
<td>profile_stationary_sf10_wide_offset_results.json</td>
<td><code>4c494a59fa793d274b0366185cfe3230b6c9fce7a57dfaa61f9f29c36465bbd3</code></td>
</tr>
</tbody>
</table>
<p>RX firmware images used, in chronological order:</p>
<table>
<thead>
<tr>
<th>Stage</th>
<th>firmware.bin SHA-256</th>
</tr>
</thead>
<tbody>
<tr>
<td>Initial nine-mode rollback</td>
<td><code>5f8dbf9c4584e0de94a7aebda5a20e961b644a880ecb6a34ab5871621958696f</code></td>
</tr>
<tr>
<td>Fixed 250 kHz offsets and traced timeout</td>
<td><code>cd839caa33c869dd448cc55e9c8b959e39d105f80a2ac4a8029393698b993fd3</code></td>
</tr>
<tr>
<td>Explicit 6 ms TCXO rollback</td>
<td><code>0ba044035c4986749c9ad4f50c702dc8c57e8e0fecf9d46fc11515cad5678166</code></td>
</tr>
<tr>
<td>Wider strict rollback</td>
<td><code>5fc919c80438635b4a96021b39fae2ada9e767508d7bb73854e4e108f0d4920f</code></td>
</tr>
<tr>
<td>Wider delivery diagnostics and fixed offsets; final installed</td>
<td><code>7b313a0f8f1eb04f6fc12197af5e9481ad43154b981ab7627e50167d2a97d8c2</code></td>
</tr>
</tbody>
</table>
<p>The 250 kHz tests used the prior nRF52 TX ZIP hash
<code>7466625ef5e7bcc8f7dd16db2b843db29b4312a33b0d32bc0b1e1193d6aee03a</code>.
All wider tests used the new selectable-spacing application:</p>
<ul>
<li>TX ZIP: <code>c474b7598a2c0b6c529ead897f3fc7aab8caf4b7581c73d7acac6ffae081377d</code></li>
<li>TX HEX: <code>b400fc53c496f4a956f88ccee5cda83b5f6679b8e2b59bfcb4b8155ea9e1e5e9</code></li>
</ul>
<p>Build artifacts are generated and may be replaced by a subsequent build;
hashes identify the images used, not a promise that every historical binary
remains in <code>.pio/build</code>. Source starts from keymindCascade commit
<code>0e5955f889788a4317863e731b38ffe09e3d5441</code> with the existing dirty changes and
these uncommitted HIL additions; this is not a clean-release comparison.</p>
</article>
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