enable MCU temp for ESP

zephcore/CMakeLists.txt

@@ -181,6 +181,13 @@ if(ZEPHCORE_PLATFORM STREQUAL "esp32")
         message(STATUS "  ESP32 CPU: 80 MHz (observers keep the SoC maximum)")
     endif()
 
+    # SoC temperature sensor (MCU temperature in telemetry, image-calibration
+    # drift on LR11xx/LR2021): every role, every SoC that has the node. The
+    # classic ESP32 (".../esp32/...") has neither the node nor a driver.
+    if(NOT BOARD MATCHES "/esp32/")
+        zephcore_add_overlay(${_zc}/esp32_coretemp.overlay)
+    endif()
+
     # Light sleep: REPEATERS on boards that declare it. 80 MHz cuts the idle draw;
     # light sleep is what removes it (mechanism and requirements:
     # boards/common/pm_esp32.conf). Repeaters only: the Espressif HCI driver takes

zephcore/adapters/board/ZephyrBoard.cpp

@@ -368,9 +368,14 @@ float ZephyrBoard::getAdcMultiplier() const
 
 float ZephyrBoard::getMCUTemperature()
 {
-	/* nRF52840 die temperature sensor - "nordic,nrf-temp" at 0x4000c000
-	 * Nodelabel "temp" is defined in nrf52840.dtsi, status="okay" by default */
+	/* SoC die temperature sensor: the `die-temp0` alias where the SoC dtsi
+	 * declares one (Espressif `coretemp`), else the nodelabel `temp` (Nordic).
+	 * NULL when the node is absent or disabled. */
+#if DT_NODE_EXISTS(DT_ALIAS(die_temp0))
+	const struct device *dev = DEVICE_DT_GET_OR_NULL(DT_ALIAS(die_temp0));
+#else
 	const struct device *dev = DEVICE_DT_GET_OR_NULL(DT_NODELABEL(temp));
+#endif
 	if (!dev || !device_is_ready(dev)) {
 		return NAN;
 	}

zephcore/boards/common/esp32_coretemp.overlay

@@ -0,0 +1,16 @@
+/*
+ * SPDX-License-Identifier: MIT
+ * ESP32-S3 / C3 / C6: enable the SoC's internal temperature sensor.
+ *
+ * Every Espressif SoC dtsi that has the sensor declares it as `coretemp`,
+ * disabled, behind the alias `die-temp0`. Enabling the node is all it takes:
+ * CONFIG_ESP32_TEMP defaults on with it, and ZephyrBoard::getMCUTemperature()
+ * finds it through the alias.
+ *
+ * Not for the classic ESP32, which has no such node (a reference to &coretemp
+ * is a dtc error there) and no driver. CMakeLists.txt skips it for that SoC.
+ */
+
+&coretemp {
+	status = "okay";
+};