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linux native Pi fixes
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@@ -5,7 +5,6 @@
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# -DEXTRA_CONF_FILE="boards/linux_native/femtofox.conf"
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# linux_common.conf/.overlay (platform base) is applied automatically.
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#
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# Source: github.com/femtofox/femtofox foxbuntu meshtasticd config
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# (femtofox_SX1262_TCXO.yaml).
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# Source: github.com/femtofox/femtofox foxbuntu (femtofox_SX1262_TCXO.yaml).
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CONFIG_ZEPHCORE_BOARD_NAME="Femtofox"
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@@ -5,7 +5,7 @@
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* Auto-paired with femtofox.conf. Defines the native_linux SPI/GPIO controllers
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* and the SX1262 radio node on top of the platform infra in linux_common.overlay.
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*
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* Pins match the meshtasticd Femtofox profile (femtofox_SX1262_TCXO.yaml):
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* Pins match the Femtofox SX1262 TCXO profile (femtofox_SX1262_TCXO.yaml):
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* gpiochip1, CS=16/GPIO48, BUSY=22/GPIO54, DIO1=23/GPIO55, RESET=25/GPIO57,
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* RXEN=24/GPIO56. DIO2 drives the RF switch, DIO3 powers a 1.8V TCXO.
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*/
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@@ -5,15 +5,12 @@
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# Raspberry Pi 5 moved the header to gpiochip4 — use rak6421_pi5.conf for it
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# (or pass --lora-gpio-chip=/dev/gpiochip4 at runtime).
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#
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# IO Slot 1 wiring (BCM GPIO numbers on gpiochip0), per meshtasticd
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# lora-RAK6421-13300-slot1.yaml:
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# IO Slot 1 wiring (BCM GPIO numbers on gpiochip0):
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# SPI: /dev/spidev0.0 (CE0 = GPIO 8, hardware CS)
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# DIO1/IRQ: GPIO 22 (IO6)
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# RESET: GPIO 16 (IO4)
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# BUSY: GPIO 24 (IO5)
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# DIO2 = RF switch, DIO3 = 1.8V TCXO, Enable_Pins 12+13 held high (GPIO hogs).
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#
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# Source: github.com/meshtastic/firmware bin/config.d/lora-RAK6421-13300-slot1.yaml
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CONFIG_ZEPHCORE_BOARD_NAME="RAK6421"
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@@ -8,8 +8,7 @@
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* Works on any Pi that exposes the 40-pin header on gpiochip0 (Pi 2/3/4/Zero 2).
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* Pi 5 moved it to gpiochip4 — use rak6421_pi5.overlay instead.
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*
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* Pins + clock mirror the authoritative meshtasticd config
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* (bin/config.d/lora-RAK6421-13300-slot1.yaml), BCM numbering:
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* Pins + clock per the RAK6421 IO Slot 1 reference wiring, BCM numbering:
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* CS = GPIO 8 (spidev0.0 CE0, hardware CS)
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* DIO1 = GPIO 22 (IO6)
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* RESET = GPIO 16 (IO4)
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@@ -19,10 +18,11 @@
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* Enable_Pins 12 + 13 are held HIGH to enable the module's RF front-end
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* (driven via GPIO hogs below — needs CONFIG_GPIO_HOGS=y, set in rak6421.conf).
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*
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* NOTE: hardware-untested in ZephCore (only the Femtofox is verified). The
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* RAK13302 (1W SKY66122) additionally wants a PA gain table that ZephCore's
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* SX126x driver does not expose; this overlay drives the 13300 correctly and
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* the 13302 at default (non-boosted) PA.
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* NOTE: hardware-verified end-to-end on a Pi Zero 2 W + RAK13300 (2026-06-03):
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* RX/TX, TCXO, and DIO2 RF switch all confirmed. The RAK13302 (1W SKY66122)
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* additionally wants a PA gain table that ZephCore's SX126x driver does not
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* expose; this overlay drives the 13300 correctly and the 13302 at default
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* (non-boosted) PA.
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*/
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#include <zephyr/dt-bindings/gpio/gpio.h>
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@@ -41,7 +41,7 @@
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ngpios = <64>;
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#gpio-cells = <2>;
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/* RAK6421 Enable_Pins (meshtasticd): held high at boot to enable
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/* RAK6421 Enable_Pins: held high at boot to enable
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* the module / RF front-end. */
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rak6421_enable {
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gpio-hog;
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@@ -58,8 +58,11 @@
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spi-mode = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* SPI CE0 = BCM GPIO 8, driven as a regular GPIO. */
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cs-gpios = <&zephcore_gpio0 8 GPIO_ACTIVE_LOW>;
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/* CS is spidev0.0's HARDWARE CE0 (BCM GPIO 8). With dtparam=spi=on
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* the kernel SPI controller owns that pin (ALT0), so it canNOT be
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* grabbed as a GPIO — spidev asserts CE0 on every transfer instead.
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* Do NOT declare cs-gpios here (that's the Femtofox path, where CS is
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* a free GPIO). */
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lora_sx1262: lora@0 {
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compatible = "semtech,sx1262";
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@@ -5,10 +5,12 @@
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* Auto-paired with rak6421_pi5.conf. Identical to rak6421.overlay except the
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* Pi 5 moved the 40-pin header GPIOs to /dev/gpiochip4.
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*
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* Pins + clock mirror meshtasticd (lora-RAK6421-13300-slot1.yaml), BCM numbering:
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* Pins + clock per the RAK6421 IO Slot 1 reference wiring, BCM numbering:
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* CS = GPIO 8 (spidev0.0 CE0), DIO1 = GPIO 22, RESET = GPIO 16, BUSY = GPIO 24,
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* DIO2 = RF switch, DIO3 = 1.8V TCXO, Enable_Pins 12+13 held high (GPIO hogs;
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* needs CONFIG_GPIO_HOGS=y in rak6421_pi5.conf). Hardware-untested in ZephCore.
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* needs CONFIG_GPIO_HOGS=y in rak6421_pi5.conf). Same wiring as rak6421.overlay,
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* which is hardware-verified on a Pi Zero 2 W (2026-06-03); the Pi 5 gpiochip4
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* variant is build-verified but not separately hardware-tested.
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*/
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#include <zephyr/dt-bindings/gpio/gpio.h>
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@@ -43,7 +45,11 @@
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spi-mode = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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cs-gpios = <&zephcore_gpio0 8 GPIO_ACTIVE_LOW>;
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/* CS is spidev0.0's HARDWARE CE0 (BCM GPIO 8). With dtparam=spi=on
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* the kernel SPI controller owns that pin (ALT0), so it canNOT be
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* grabbed as a GPIO — spidev asserts CE0 on every transfer instead.
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* Do NOT declare cs-gpios here (that's the Femtofox path, where CS is
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* a free GPIO). */
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lora_sx1262: lora@0 {
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compatible = "semtech,sx1262";
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