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https://github.com/liquidraver/ZephCore.git
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core: restore upstream shape for the shared mesh core
- Mesh, Dispatcher, Packet, packet pool and the core headers rebuilt from Arduino MeshCore's text; ZephCore changes re-applied, each fenced `// ZEPHCORE:` (diff vs upstream: 4540 -> 1147 lines) - upstream header layout; MainBoard gains handleCommand/loop and the other upstream members; RNG::nextInt back in Utils.cpp - packet logging moved to the roles' log hooks (helpers/PacketLog.h) - zero-hop direct ACKs deduplicated and length-checked as upstream - RadioIncludes.h -> src/, LoRaConfig.h -> helpers/ - .editorconfig: shared files keep upstream formatting Verified: 10 role builds, per-function disassembly review, bench DM/ACK regression (T1000-E, Wio L1, XIAO S3 on 1.17.4) incl. via live repeater.
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@@ -14,6 +14,16 @@ LOG_MODULE_REGISTER(zephcore_utils, CONFIG_ZEPHCORE_MAIN_LOG_LEVEL);
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namespace mesh {
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uint32_t RNG::nextInt(uint32_t _min, uint32_t _max)
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{
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uint32_t num;
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random((uint8_t *)&num, sizeof(num));
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if (_max <= _min) { /* ZEPHCORE: no modulo by zero */
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return _min;
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}
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return (num % (_max - _min)) + _min;
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}
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static uint8_t hexVal(char c)
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{
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if (c >= 'A' && c <= 'F') return c - 'A' + 10;
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@@ -258,6 +268,16 @@ bool Utils::fromHex(uint8_t *dest, int dest_size, const char *src_hex)
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return true;
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}
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bool Utils::isZeroes(const uint8_t *buf, size_t len)
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{
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while (len > 0) {
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if (*buf != 0) return false;
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buf++;
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len--;
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}
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return true;
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}
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bool Utils::isHexChar(char c)
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{
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return (c >= '0' && c <= '9') || (c >= 'A' && c <= 'F') || (c >= 'a' && c <= 'f');
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