89 Commits
Author SHA1 Message Date
liquidraver ba33cebf6a cad improvements 2026-09-01 22:05:29 +02:00
liquidraver 5bf3c577c9 tune cad detection across all chips 2026-08-29 17:31:39 +02:00
liquidraver ea86815c95 fix LNA/FEM control 2026-08-25 14:04:32 +02:00
liquidraver da141327d7 radio driver fixes v2 2026-08-24 10:35:49 +02:00
liquidraver dc5b5c2594 radio driver fixes v1 2026-08-23 22:49:17 +02:00
liquidraver d6a78e5d92 upstream sweep 2026-08-23 15:56:08 +02:00
liquidraver 174bce80d9 cleanup/bugfix run 2026-08-23 09:45:14 +02:00
liquidraver 7d695872d4 implement radio.fem.rxgain 2026-08-22 17:32:41 +02:00
liquidraver 5c4ac21bd4 refactor patches and bump to 1.17.2 2026-08-20 17:50:48 +02:00
liquidraver 4473b261ee rx path fixes, dc.restart wired in to lr chips,
TX timeout magic number is gone
2026-08-14 13:27:54 +02:00
liquidraver c45e7ae774 second audit sweep 2026-08-14 11:05:52 +02:00
liquidraver ff0db0dcb8 lr2021 debug v2 2026-08-14 08:36:36 +02:00
liquidraver aac97f7ade vcontact and cad fixes 2026-08-12 15:36:51 +02:00
liquidraver ee90693c89 lr20xx: add freq-error summary log and get freqerr CLI 2026-08-12 15:12:43 +02:00
liquidraver 3a3ac3df2e lr20xx: expose per-packet frequency error and fix the duty-cycle wake budget 2026-08-12 14:55:16 +02:00
liquidraver b839c2c5d1 bump lr sdk and audit refactor 2026-08-12 14:40:52 +02:00
liquidraver 101e97f54a lr20xx: bump vendored SDK to v2.0.2 and load the firmware Patch RAM 2026-08-11 22:36:31 +02:00
liquidraver ab03be110e wrapup lr2021 session 2026-08-11 16:47:21 +02:00
liquidraver b27f5e0625 x1 duty cycle debug 2026-08-11 15:58:59 +02:00
liquidraver 3494411f83 x1 debug 2026-08-10 19:15:26 +02:00
liquidraver 9f66e9749c x1 debug v1 2026-08-10 08:32:43 +02:00
liquidraver 17dfa78629 sync lr2021 with radiolib commits 2026-08-07 14:17:05 +02:00
liquidraver d1093bfc5e gps "fiddling" v2 and some debug log fixes 2026-08-05 11:48:33 +02:00
liquidraver 3e534e6239 probing improvements 2026-07-29 15:27:26 +02:00
liquidraver a705d5b5ce refactor / unify probes 2026-07-29 12:30:47 +02:00
liquidraver fe6e585eb6 get rid of housekeeping tick and AGC reset 2026-07-28 14:12:40 +02:00
liquidraver 06a0b03a20 LR1110 duty cycle finally and zephyr PM vs UART wedge fixes 2026-07-25 11:27:25 +02:00
liquidraver 13b5e2fcf3 scrub APC and bump to 1.16.6 2026-07-20 09:55:32 +02:00
liquidraver 432336867b add cad.busycap knob for hilltop repeaters 2026-07-13 10:29:50 +02:00
liquidraver 9eb33e27dc cad, meshamerica flasher and other polishes 2026-07-13 09:00:14 +02:00
liquidraver a320a7646d SmartCAD p2 2026-07-12 14:18:07 +02:00
liquidraver dc1239537e SmartCAD p1 2026-07-12 10:48:37 +02:00
Étienne Fesser c4fb9c0638 Fix TX wait thread stack overflow on Xtensa (boot freeze)
TX_WAIT_THREAD_STACK_SIZE was 1024 bytes, shared by every radio
adapter. On Xtensa (all ESP32/S3 boards) the windowed ABI needs ~3x
the stack of Cortex-M for the same code — Zephyr's own Kconfig
defaults reflect this (IDLE_STACK_SIZE: 1024 if XTENSA vs 320 ARM).

Measured peak usage on Heltec V4 (immediate-mode logging, full TX
cycle including startReceive/lora_config): 1252 bytes — already past
the old 1024 limit. The overflow corrupts the exception frame and
parks CPU0 in _DoubleExceptionVector (LoadProhibited @0x2c), a silent
total freeze at boot. Confirmed via the S3 built-in USB-JTAG:
current thread at crash = lora_tx_wait.

2048 gives ~39% headroom over the measured worst case.
2026-07-06 19:26:17 +02:00
liquidraver 6ef03fb10e Merge branch 'master' into dev 2026-07-03 19:58:07 +02:00
liquidraver fc940d27ba sync with dev 2026-07-02 13:13:26 +02:00
Matthew Burton 43f455393e added colour and fixed set tx adc not sticking 2026-06-29 20:22:52 +02:00
liquidraver bf71542751 Make Rxdutycycling Great Again 2026-06-13 08:23:01 +02:00
liquidraver 2ad185bab4 license "refactor" :) 2026-06-07 22:47:17 +02:00
liquidraver 4353936328 lr2021 experiments 2026-06-06 15:33:37 +02:00
liquidraver 7d7a64ff5a fix: airtime LDRO threshold must track driver (was BW-blind sf>=11)
getEstAirtimeFor() set LDRO from `sf >= 11`, correct only at BW125. Now
matches the driver's should_enable_ldro() (t_sym > 16.38 ms) so the
estimate's DE tracks hardware DE on every SF/BW. Also drop dead
calcRxDelay() + unused MAX_RX_DELAY_MILLIS.
2026-05-29 15:48:48 +02:00
liquidraver 66fc25557d simplify LoRaRadioBase: merge configureRx/Tx into configure(bool) 2026-05-29 13:51:49 +02:00
liquidraver 3441caf8b0 new rx busy latch 2026-05-14 22:24:48 +02:00
liquidraver 6919c3511c rx_boost state is undefined at boot (minor fix)
every LBT-retried flood packet loses its priority (fixed)
witching between LBT and non-LBT mode (or any cad.mode change) could silently skip full reconfiguration and leave the radio in the wrong mode (fixed)
2026-05-08 09:50:52 +02:00
liquidraver 2a8cc88262 fix fast path LBT CAD mode 2026-05-07 11:37:09 +02:00
liquidraverandClaude Opus 4.7 5e7adfb130 normalize source-file line endings to LF
Add .gitattributes rules so .c/.h/.cpp/.hpp are always stored as LF
(prevents EOL drift from editors with autocrlf-true defaults), and
renormalize the 30 source files that had drifted to CRLF in the index.

Pure mechanical change — `git diff --ignore-cr-at-eol` is empty.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
2026-05-05 14:56:44 +02:00
liquidraver e8f14442bf ramp time to 800us and duty cycle to 13/3 2026-05-05 14:52:05 +02:00
liquidraver ee2990fd16 hwconfig failsafe and duty cycle 10/6->10/4 (tests showed better reception) 2026-05-05 10:46:58 +02:00
liquidraver 9a1569c511 make rx duty cycle tuning more easy 2026-05-04 15:09:26 +02:00
liquidraver 1a956aa86a remove hot path RX, re-done the math, solves nothing, eats battery 2026-05-02 12:13:29 +02:00
liquidraver 9282ac8c9c stay in full RX after TX for 3 seconds
agc reset on every lora_recv_duty_cycle entry
2026-05-01 20:46:12 +02:00