mirror of
https://github.com/liquidraver/ZephCore.git
synced 2026-09-04 14:33:56 +00:00
32 lines
1.4 KiB
Plaintext
32 lines
1.4 KiB
Plaintext
# nRF54L Platform Configuration
|
|
# Included by all nRF54L-based boards (XIAO nRF54L15, etc.)
|
|
# Only contains nRF54L-specific settings — common BLE/Storage/Input is in zephcore_common.conf
|
|
#
|
|
# Include order: prj.conf → zephcore_common.conf → nrf54l_common.conf → <board>/board.conf
|
|
#
|
|
# NOTE: nRF54L15 has NO native USB.
|
|
# XIAO nRF54L15 has a SAMD11 bridge chip (CMSIS-DAP) that converts UART20 → USB CDC
|
|
# on the host side. Flashing is via SWD through CMSIS-DAP (west flash / openocd).
|
|
|
|
# ========== CPU Clock: DVFS low (64 MHz) for power saving ==========
|
|
# nRF54L15 supports 64/128/320 MHz via HSFLL DVFS.
|
|
# 64 MHz is plenty for event-driven companion firmware.
|
|
CONFIG_CLOCK_CONTROL_NRF_HSFLL_LOCAL_REQ_LOW_FREQ=y
|
|
|
|
# ========== BLE: nRF54L-specific controller settings ==========
|
|
# TX power: +8 dBm (max — same open-source BLE controller as nRF52)
|
|
CONFIG_BT_CTLR_TX_PWR_PLUS_8=y
|
|
|
|
# Data Length Extension — controller-side max
|
|
CONFIG_BT_CTLR_DATA_LENGTH_MAX=251
|
|
|
|
# Coded PHY — enable in nRF LL controller (host auto-request in zephcore_common.conf)
|
|
CONFIG_BT_CTLR_PHY_CODED=y
|
|
|
|
# ========== Debug ==========
|
|
# SEGGER RTT and CONFIG_ASSERT are debug-only and live in boards/common/debug.conf
|
|
# (opt-in). Keeping them here would override the production defaults from
|
|
# prj.conf on every nRF54L build, since this file loads after prj.conf.
|
|
# BT_CTLR_ASSERT_HANDLER is harmless when CONFIG_ASSERT=n, so it stays on.
|
|
CONFIG_BT_CTLR_ASSERT_HANDLER=y
|