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56 lines
2.6 KiB
Plaintext
56 lines
2.6 KiB
Plaintext
# STM32WL Platform Configuration (Seeed LoRa-E5 / STM32WLE5JC)
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#
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# Included by all STM32WL boards. STM32WL has NO Bluetooth radio and NO USB
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# peripheral, so these boards are UART-only: the repeater CLI (and the serial
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# companion) run over USART1 (chosen zephyr,console) through the board's
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# onboard USB-UART bridge. Flashing is over SWD/ST-Link (west flash / OpenOCD).
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#
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# Include order: prj.conf -> zephcore_common.conf -> stm32wl_common.conf -> board.conf
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# Only contains STM32WL-specific settings; common app/crypto/storage is in
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# zephcore_common.conf.
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# ========== Boot / Flash layout ==========
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# No MCUboot: the application links at the flash origin via the single
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# slot0_partition defined in board.overlay (zephyr,code-partition).
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CONFIG_USE_DT_CODE_PARTITION=y
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# ========== No Bluetooth ==========
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# STM32WL has no BLE radio. Disabling here makes every build on this platform
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# BT-free (the companion transport is serial, not NUS). Mirrors repeater.conf.
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CONFIG_BT=n
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# ========== No USB device stack ==========
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# STM32WLE5JC has no USB peripheral. Console/CLI is plain UART
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# (UART_INTERRUPT_DRIVEN already set in prj.conf). No UF2 output.
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# ========== Entropy / CSPRNG ==========
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# STM32WL provides only a raw TRNG (st,stm32-rng), not a hardware CSPRNG.
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# Enable the TRNG as the entropy source; with an entropy driver present,
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# CONFIG_CSPRNG_ENABLED defaults y and sys_csrand_get() is backed by the
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# hardware CS generator. ZephyrRNG additionally conditions identity seeds with
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# CPU-jitter + AES-256-CTR (see adapters/rng/ZephyrRNG.cpp), so a weak/slow
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# TRNG cannot silently produce correlated keys. CONFIG_CSPRNG_ENABLED (which
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# ZephyrRNG BUILD_ASSERTs on) is not directly assignable -- it defaults y once
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# an entropy driver is present (subsys/random/Kconfig), so enabling the TRNG
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# below is sufficient.
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CONFIG_ENTROPY_GENERATOR=y
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CONFIG_ENTROPY_STM32_RNG=y
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# ========== Memory (64KB SRAM / 256KB flash) ==========
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# RAM is the binding constraint on STM32WL (flash sits at ~63%), so spend the
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# abundant flash to reclaim SRAM.
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#
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# AES lookup tables in ROM: the tf-psa-crypto builtin AES otherwise computes
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# ~8KB of forward/reverse tables (RT0..RT3, RSb, ...) into .bss at runtime.
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# ROM_TABLES makes them const (flash) instead. Single biggest SRAM win here.
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CONFIG_MBEDTLS_AES_ROM_TABLES=y
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# PSA key slots: default 16 each cost ~40B+ of static slot state. The mesh only
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# juggles a couple of ephemeral AES keys at once; 8 is ample.
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CONFIG_MBEDTLS_PSA_KEY_SLOT_COUNT=8
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# Trim the common 8KB stacks to fit 64KB SRAM. Crypto (Ed25519/PSA) and the
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# RNG jitter sampler run on the main thread, so keep main comfortable.
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CONFIG_MAIN_STACK_SIZE=6144
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CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096
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