mirror of
https://github.com/liquidraver/ZephCore.git
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58 lines
1.8 KiB
Plaintext
58 lines
1.8 KiB
Plaintext
/*
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* SPDX-License-Identifier: MIT
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*
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* Femtofox (Luckfox Pico Mini RV1103 + Ebyte E22-900M30S, SX1262 TCXO) wiring.
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* Auto-paired with femtofox.conf. Defines the native_linux SPI/GPIO controllers
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* and the SX1262 radio node on top of the platform infra in linux_common.overlay.
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*
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* Pins match the Femtofox SX1262 TCXO profile (femtofox_SX1262_TCXO.yaml):
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* gpiochip1, CS=16/GPIO48, BUSY=22/GPIO54, DIO1=23/GPIO55, RESET=25/GPIO57,
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* RXEN=24/GPIO56. DIO2 drives the RF switch, DIO3 powers a 1.8V TCXO.
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*/
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/lora/sx126x.h>
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/ {
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aliases {
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/* The mesh adapter reads lora0 to bind the SX126x driver. */
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lora0 = &lora_sx1262;
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};
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/* GPIO V2 chardev controller bound to /dev/gpiochip1. */
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zephcore_gpio0: zephcore_gpio0 {
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status = "okay";
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compatible = "zephcore,gpio-native-linux";
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gpio-controller;
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gpio-chip = "/dev/gpiochip1";
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ngpios = <64>;
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#gpio-cells = <2>;
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};
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/* spidev-backed SPI bus on /dev/spidev0.0 with one SX1262 child. */
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zephcore_spi0: zephcore_spi0 {
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status = "okay";
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compatible = "zephcore,spi-native-linux";
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spi-dev = "/dev/spidev0.0";
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clock-frequency = <2000000>;
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spi-mode = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* CS: gpiochip1 offset 16 = GPIO48. */
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cs-gpios = <&zephcore_gpio0 16 GPIO_ACTIVE_LOW>;
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lora_sx1262: lora@0 {
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compatible = "semtech,sx1262";
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reg = <0>;
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spi-max-frequency = <2000000>;
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reset-gpios = <&zephcore_gpio0 25 GPIO_ACTIVE_LOW>;
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busy-gpios = <&zephcore_gpio0 22 GPIO_ACTIVE_HIGH>;
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dio1-gpios = <&zephcore_gpio0 23 GPIO_ACTIVE_HIGH>;
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rx-enable-gpios = <&zephcore_gpio0 24 GPIO_ACTIVE_HIGH>;
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dio2-tx-enable;
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dio3-tcxo-voltage = <SX126X_DIO3_TCXO_1V8>;
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tcxo-power-startup-delay-ms = <5>;
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};
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};
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};
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