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ZephCore/zephcore/boards/common/rtc-i2c.dtsi
T
Pieter ViljoenandClaude Opus 5.5 26217825b3 rtc: write the RX8130CE and YSN8900 weekday one-hot
rtc_time_block() wrote the weekday as a number 0-6 (Sunday 0) for every
RTC. The RX8130CE's WEEK register (13h) is one-hot: Epson ETM50E-10
14.1.2, Table 15, p. 27, Sunday 01h to Saturday 40h, with no more than
one bit set. So each sync wrote Sunday as no day, Monday as Sunday, and
Wednesday, Friday and Saturday as two days at once. ZephCore never
reads the weekday back, so its time and date were unaffected.

A new boolean descriptor property, weekday-one-hot, is set on the
RX8130CE node in rtc-i2c.dtsi, and rtc_time_block() writes BIT(dow)
where it is set. That is the encoding of Zephyr's rtc_rx8130ce.c. The
DS3231, PCF8563 and RV3028 keep 0-6, as Zephyr's drivers for them
write it. The binding and comments no longer call the whole block BCD.

meshtracker_x1's YSN8900 sets it too. The board already uses the RX8900
register map for it, and the RX8900's WEEK register (03h) is one-hot:
Epson ETM45E-11 8.2.2, Table 15, p. 16. The YSN8900's own data sheet
has no register map, and its programming guide is not available.

The same defect and fix as meshcore-dev/MeshCore#3550.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-05 12:35:32 -07:00

84 lines
3.3 KiB
Devicetree

/*
* Common I2C Real-Time-Clock descriptors for ZephCore
* SPDX-License-Identifier: MIT
*
* OPT-IN: include this inside an &i2cN { ... } block ONLY on boards that
* physically have a battery/cap-backed RTC. Kept separate from
* sensors-i2c.dtsi because these declare fixed I2C addresses (0x68/0x51/
* 0x52/0x32) that collide with common parts — an IMU/accelerometer sits at
* 0x68 (same as DS3231). Including this on a board without an RTC would risk
* a devicetree unit-address clash and a runtime mis-probe, so it is opt-in.
*
* Usage (board overlay/dts, alongside the sensors include):
* &i2c0 {
* #include "../../common/sensors-i2c.dtsi"
* #include "../../common/rtc-i2c.dtsi"
* };
*
* These bind NO Zephyr RTC driver — they're data-only descriptors the
* boot-time auto-discovery (adapters/clock/ZephyrRTCDiscover.c) probes via
* raw I2C to restore wall-clock time at boot. A chip that isn't actually
* present fails the probe and is skipped. One chip per I2C address:
*
* Chip │ Addr │ Also covers (same regs)
* ──────────┼──────┼─────────────────────────
* DS3231 │ 0x68 │ DS1307, DS3232
* PCF8563 │ 0x51 │ — (PCF85063A is 0x51 too but differs — override)
* RV3028 │ 0x52 │ —
* RX8130CE │ 0x32 │ — (RV8803 is 0x32 too but differs — override)
*
* status-reg 0xFF means the power-loss flag is in the seconds byte. A board
* with a same-address variant should /delete-node/ the conflicting one and
* add its own in the board overlay.
*/
rtc_ds3231: rtc-ds3231@68 {
compatible = "zephcore,rtc-i2c";
reg = <0x68>;
time-reg = <0x00>;
date-index = <4>;
status-reg = <0x0F> /* control/status */
status-mask = <0x80> /* OSF — oscillator stopped */
/* Bits shown as 0 in all three parts: DS3231 (19-5170 Rev 10, Figure 1,
* p. 11) and DS3232 (19-5337 Rev 5, Figure 1, p. 11), where 05h bit 7 is
* Century, and DS1307 (Rev 3/15, Table 2, p. 8, "always reads back as
* 0"). 00h bit 7 is left out: it is the DS1307's clock-halt bit, set on
* a new chip. On a DS1307, 0Fh is RAM, so status-reg reads a user byte. */
zero-mask = [00 80 80 f8 c0 60 00];
};
rtc_pcf8563: rtc-pcf8563@51 {
compatible = "zephcore,rtc-i2c";
reg = <0x51>;
time-reg = <0x02>;
date-index = <3>; /* PCF8563 puts date before weekday */
status-reg = <0xFF> /* flag is in the seconds byte */
status-mask = <0x80> /* VL — clock integrity not guaranteed */
/* No zero-mask: the data sheet (Rev. 11.1, Table 4, p. 10) marks the
* unused bits "not relevant", not 0. */
};
rtc_rv3028: rtc-rv3028@52 {
compatible = "zephcore,rtc-i2c";
reg = <0x52>;
time-reg = <0x00>;
date-index = <4>;
status-reg = <0x0e> /* status */
status-mask = <0x01> /* PORF — power-on reset */
/* RV-3028-C7 Application Manual Rev. 1.4, 3.2, p. 12 */
zero-mask = [80 80 c0 f8 c0 e0 00];
};
rtc_rx8130ce: rtc-rx8130ce@32 {
compatible = "zephcore,rtc-i2c";
reg = <0x32>;
time-reg = <0x10>;
date-index = <4>;
status-reg = <0x1d> /* flag */
status-mask = <0x02> /* VLF — voltage low */
/* RX8130CE Application Manual ETM50E-10, 13.2.1 Table 12, p. 22 */
zero-mask = [80 80 c0 80 c0 e0 00];
/* 14.1.2 Table 15, p. 27: Sunday 01h ... Saturday 40h */
weekday-one-hot;
};