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27 lines
1.0 KiB
Plaintext
27 lines
1.0 KiB
Plaintext
# EFR32MG24 Platform Configuration
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# Included by all MG24-based boards (XIAO MG24, etc.)
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# Only contains MG24-specific settings — common BLE/Storage/Input is in zephcore_common.conf
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#
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# Include order: prj.conf → zephcore_common.conf → mg24_common.conf → <board>/board.conf
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#
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# NOTE: MG24 uses Silicon Labs proprietary BLE controller blob.
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# Requires: west blobs fetch hal_silabs
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# ========== BLE: MG24-specific controller settings ==========
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# DLE managed internally by Silabs blob — no CONFIG_BT_CTLR_DATA_LENGTH_MAX
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# TX power managed internally by Silabs blob — no CONFIG_BT_CTLR_TX_PWR_*
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# BLE thread stacks — Silabs blob needs larger stacks
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CONFIG_BT_TX_PROCESSOR_STACK_SIZE=2048
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# Controller assert handler — without this, a controller assert silently
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# freezes the CPU at highest IRQ priority with zero log output.
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CONFIG_BT_CTLR_ASSERT_HANDLER=y
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# ========== Debug ==========
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CONFIG_ASSERT=y
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# ========== Heap ==========
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# Silabs BLE stack requires larger heap (override zephcore_common 2KB default)
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CONFIG_HEAP_MEM_POOL_SIZE=32768
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