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34 lines
1.3 KiB
Plaintext
34 lines
1.3 KiB
Plaintext
# nRF54L Platform Configuration
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# Included by all nRF54L-based boards (XIAO nRF54L15, etc.)
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# Only contains nRF54L-specific settings — common BLE/Storage/Input is in zephcore_common.conf
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#
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# Include order: prj.conf → zephcore_common.conf → nrf54l_common.conf → <board>/board.conf
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#
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# NOTE: nRF54L15 has NO native USB.
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# XIAO nRF54L15 has a SAMD11 bridge chip (CMSIS-DAP) that converts UART20 → USB CDC
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# on the host side. Flashing is via SWD through CMSIS-DAP (west flash / openocd).
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# ========== CPU Clock: DVFS low (64 MHz) for power saving ==========
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# nRF54L15 supports 64/128/320 MHz via HSFLL DVFS.
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# 64 MHz is plenty for event-driven companion firmware.
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CONFIG_CLOCK_CONTROL_NRF_HSFLL_LOCAL_REQ_LOW_FREQ=y
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# ========== BLE: nRF54L-specific controller settings ==========
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# TX power: +4 dBm (same open-source BLE controller as nRF52)
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CONFIG_BT_CTLR_TX_PWR_PLUS_4=y
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# Data Length Extension — controller-side max
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CONFIG_BT_CTLR_DATA_LENGTH_MAX=251
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# Coded PHY — enable in nRF LL controller (host auto-request in zephcore_common.conf)
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CONFIG_BT_CTLR_PHY_CODED=y
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# ========== SEGGER RTT (J-Link / CMSIS-DAP debug) ==========
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CONFIG_LOG_BACKEND_RTT=y
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CONFIG_USE_SEGGER_RTT=y
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CONFIG_SEGGER_RTT_BUFFER_SIZE_UP=4096
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# ========== Debug ==========
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CONFIG_ASSERT=y
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CONFIG_BT_CTLR_ASSERT_HANDLER=y
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