From 9d0d58ca4b4f9b78b6690e14853be465aeb3e3bf Mon Sep 17 00:00:00 2001
From: dxl <64101226@qq.com>
Date: Sat, 10 Oct 2026 09:29:15 +0800
Subject: [PATCH] FPGA: hi_sniffer.v merged.

---
 fpga/hi_sniffer.v | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/fpga/hi_sniffer.v b/fpga/hi_sniffer.v
index 8f97550a7..3ca0a8691 100644
--- a/fpga/hi_sniffer.v
+++ b/fpga/hi_sniffer.v
@@ -50,16 +50,34 @@ always @(posedge ssp_clk)
 begin
     ssp_cnt <= ssp_cnt + 1'b1;
 
+`ifdef WITH_TIMODE
+    if(ssp_cnt[2:0] == 3'b111) // set frame pin to high for TI mode on the last bit of the frame
+    begin
+        ssp_frame <= 1'b1;
+    end
+`endif
+
     if(ssp_cnt[2:0] == 3'b000) // set frame length
     begin
         adc_d_out[7:0] <= adc_d;
-        ssp_frame <= 1'b1;
+
+`ifdef WITH_TIMODE
+        ssp_frame <= 1'b0; // In TI mode, pull the frame signal low here—at the rising edge of the first bit (marking the end of the last bit).
+`else
+        ssp_frame <= 1'b1; // In SSP mode, pull the frame signal high here.
+`endif
+
     end
+
     else
     begin
         // shift value right one bit
         adc_d_out[7:0] <= {1'b0, adc_d_out[7:1]};
-        ssp_frame <= 1'b0;
+
+`ifndef WITH_TIMODE
+        ssp_frame <= 1'b0; // In SSP mode, pull the frame signal low here.
+`endif
+
     end
 
 end