dxl da413ac9b9 Merge branch 'master' into fpga-merge-and-opensource ...

# Conflicts:
#	fpga/hi_flite.v

2026-10-12 00:22:24 +08:00

..

tests

Unified fpga folders

2023-05-30 19:47:27 +02:00

clk_divider.v

FPGA: Specify the bit width to comply with the [IEEE 1364] standard to resolve synthesis tool warnings.

2026-10-09 11:33:10 +08:00

define.v

FPGA: Added 'FPGA_CMD_SET_PWR_PWM_LOW_COUNT' cmd on PM5 platform.

2026-10-09 11:43:59 +08:00

fpga_icopyx_felica.bit

Unified fpga folders

2023-05-30 19:47:27 +02:00

fpga_icopyx_hf_15.bit

Unified fpga folders

2023-05-30 19:47:27 +02:00

fpga_icopyx_hf.bit

add bitfiles for prox ultimate build

2025-06-08 06:26:33 +01:00

fpga_icopyx_hf.v

Make detection threshold for ISO14443A configurable

2024-02-02 20:51:05 +01:00

fpga_icopyx_lf.bit

Unified fpga folders

2023-05-30 19:47:27 +02:00

fpga_icopyx_lf.v

Whitespace, formatting

2023-08-24 18:21:07 +02:00

fpga_icopyx_top.v

Removed commented out includes

2023-08-24 18:06:44 +02:00

fpga_pm3_felica.bit

hf felica: make reading actually work

2026-08-28 22:35:08 +02:00

fpga_pm3_hf_15.bit

change seed, making new iclass builds work again

2025-06-04 22:03:56 +01:00

fpga_pm3_hf.bit

change seed, making new iclass builds work again

2025-06-04 22:03:56 +01:00

fpga_pm3_lf.bit

hitag2: fix simulation against genuine readers, add restore, fix info

2026-09-04 13:20:29 +02:00

fpga_pm3_top.v

hitag2: fix simulation against genuine readers, add restore, fix info

2026-09-04 13:20:29 +02:00

fpga_pm3_ult_felica.bit

add bitfiles for prox ultimate build

2025-06-08 06:26:33 +01:00

fpga_pm3_ult_hf_15.bit

add bitfiles for prox ultimate build

2025-06-08 06:26:33 +01:00

fpga_pm3_ult_hf.bit

add bitfiles for prox ultimate build

2025-06-08 06:26:33 +01:00

fpga_pm3_ult_lf.bit

add bitfiles for prox ultimate build

2025-06-08 06:26:33 +01:00

fpga_pm5_hf.v

FPGA: Add source files specific to PM5.

2026-10-12 00:04:06 +08:00

fpga_pm5_lf.v

FPGA: Add source files specific to PM5.

2026-10-12 00:04:06 +08:00

fpga_pm5_top.v

FPGA: Add source files specific to PM5.

2026-10-12 00:04:06 +08:00

gowin_rpll.v

FPGA: Add source files specific to PM5.

2026-10-12 00:04:06 +08:00

hi_flite.v

Merge branch 'master' into fpga-merge-and-opensource

2026-10-12 00:22:24 +08:00

hi_get_trace.v

FPGA: hi_get_trace.v merged.

2026-10-09 18:26:38 +08:00

hi_iso14443a.v

FPGA: rename all ssp frame set/clr definition.

2026-10-10 16:08:27 +08:00

hi_reader.v

FPGA: Added a TODO in hi_reader.v

2026-10-11 23:43:32 +08:00

hi_simulate.v

FPGA: rename all ssp frame set/clr definition.

2026-10-10 16:08:27 +08:00

hi_sniffer.v

FPGA: hi_sniffer.v merged.

2026-10-10 09:29:15 +08:00

lf_edge_detect.v

hitag2: fix simulation against genuine readers, add restore, fix info

2026-09-04 13:20:29 +02:00

lo_adc.v

Merge branch 'master' into fpga-merge-and-opensource

2026-10-12 00:22:24 +08:00

lo_edge_detect.v

Merge branch 'master' into fpga-merge-and-opensource

2026-10-12 00:22:24 +08:00

lo_passthru.v

Unified fpga folders

2023-05-30 19:47:27 +02:00

lo_read.v

FPGA: lo_read.v merged.

2026-10-10 16:00:06 +08:00

lo_simulate.v

Unified fpga folders

2023-05-30 19:47:27 +02:00

lp20khz_1MSa_iir_filter.v

FPGA: Specify the bit width to comply with the [IEEE 1364] standard to resolve synthesis tool warnings.

2026-10-09 11:33:10 +08:00

Makefile

Merge branch 'master' into fpga-merge-and-opensource

2026-10-12 00:22:24 +08:00

min_max_tracker.v

hitag2: fix simulation against genuine readers, add restore, fix info

2026-09-04 13:20:29 +02:00

mux2_onein.v

Removed commented out includes

2023-08-24 18:06:44 +02:00

mux2_oneout.v

Removed commented out includes

2023-08-24 18:06:44 +02:00

mux8.v

Removed commented out includes

2023-08-24 18:06:44 +02:00

mux16.v

Removed commented out includes

2023-08-24 18:06:44 +02:00

strip_date_time_from_binary.py

code style

2025-02-21 16:33:40 +01:00

xc2s30-5-vq100.ucf

Unified fpga folders

2023-05-30 19:47:27 +02:00

xc2s50-5-tq144.ucf

Add files via upload

2024-12-03 21:04:50 +08:00

xc3s100e-4-vq100.ucf

Unified fpga folders

2023-05-30 19:47:27 +02:00