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https://github.com/RfidResearchGroup/proxmark3.git
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117 lines
3.4 KiB
C
117 lines
3.4 KiB
C
#ifndef SYS_HW_AT32_H
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#define SYS_HW_AT32_H
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#include "common.h"
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#include "at32f435_437_misc.h"
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#include "at32f435_437_crm.h"
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#include "at32f435_437_pwc.h"
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/**
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* What's method for system reset we are using?
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* 0(default): system_simple_reset() + jump to bootrom
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* 1: nvic_system_reset() [NOT IMPLEMENT]
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*/
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extern uint8_t g_system_reset_method;
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// --- Handlers
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void NMI_Handler(void);
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void HardFault_Handler(void);
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void MemManage_Handler(void);
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void BusFault_Handler(void);
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void UsageFault_Handler(void);
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void SVC_Handler(void);
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void DebugMon_Handler(void);
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void PendSV_Handler(void);
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void SysTick_Handler(void);
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// ---
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void system_clock_config_48m(void);
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void system_clock_config_288m(void);
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void system_simple_reset(void);
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bool system_bpr_chk_clear(void);
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STATIC_FORCE_INLINE main_chip_type_t GetChipType(void) {
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return MAIN_CHIP_TYPE_AT32;
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}
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STATIC_FORCE_INLINE uint32_t GetChipId(void) {
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// DEBUG_IDCODE
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return *((uint32_t *) 0xE0042000);
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}
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STATIC_FORCE_INLINE uint8_t *GetChipUniqueId(uint8_t *size) {
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// See: Unique device ID register, doc 1.3.2
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// The unique device ID is a 96-bit value that is programmed by the manufacturer.
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// It is used to uniquely identify each device and can be used for various purposes such as licensing, security, and tracking.
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if (size) {
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*size = 12; // 96 bits = 12 bytes
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}
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return (uint8_t *) 0x1FFFF7E8;
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}
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STATIC_FORCE_INLINE void ResetChip(void) {
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// Which reset method should be used?
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if (g_system_reset_method == 0) {
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// Call system_simple_reset() to simply reset the state of most peripherals, and jump to boot.
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system_simple_reset();
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} else {
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// On current hardware, resetting the NVIC will cause the ARM_POWER_ON pin to return to input mode. However,
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// it takes 10ms to 25ms from RESET to startup, during which time the device has already been powered off.
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// If future hardware support keeping the GPIO level of ARM_POWER_ON during RESET, then NVIC reset can be enabled.
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nvic_system_reset();
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}
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}
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STATIC_FORCE_INLINE uint32_t GetChipFlashSize(void) {
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// See: Flash capacity register, doc 1.3.1
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// Flash storage capacity, measured in KBytes
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// For example: 0x0080 = 128KByte
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return *((uint32_t *) 0x1FFFF7E0) * 1024; // '<< 10' or '* 1024', Best to reduce the difficulty of understanding.
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}
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STATIC_FORCE_INLINE bool CheckRSTWithSRAMRetention(void) {
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if (system_bpr_chk_clear()) {
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crm_flag_clear(CRM_ALL_RESET_FLAG);
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return true;
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}
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// If enter Standby Mode, the sram will power off.
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if (CRM->ctrlsts_bit.lprstf && PWC->ctrlsts_bit.swef && PWC->ctrlsts_bit.sef) {
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crm_flag_clear(CRM_ALL_RESET_FLAG);
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return false;
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}
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// WDT reset & WWDT reset
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if (CRM->ctrlsts_bit.wwdtrstf || CRM->ctrlsts_bit.wdtrstf) {
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crm_flag_clear(CRM_ALL_RESET_FLAG);
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return true;
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}
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// CPU software reset
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if (CRM->ctrlsts_bit.swrstf) {
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crm_flag_clear(CRM_ALL_RESET_FLAG);
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return true;
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}
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// NRST reset (pin)
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// When powered on for the first time, nrstf will also be set, which we need to confirm together with por.
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if (CRM->ctrlsts_bit.nrstf && CRM->ctrlsts_bit.porrstf == 0 && CRM->ctrlsts_bit.swrstf == 0) {
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crm_flag_clear(CRM_ALL_RESET_FLAG);
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return true;
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}
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// POR/LVR reset flag? Or otherwise case...
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crm_flag_clear(CRM_ALL_RESET_FLAG);
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return false;
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}
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#endif //SYS_HW_AT32_H
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