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https://github.com/mikecarper/MeshCore.git
synced 2026-10-24 22:02:25 +00:00
Resolve HIL USB device links before setting modem signals
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commit
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2 files changed
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@@ -3,6 +3,7 @@
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import argparse
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import json
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import itertools
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import os
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import secrets
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from pathlib import Path
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import time
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@@ -14,10 +15,12 @@ _run_sequences = itertools.count(secrets.randbelow(0x3fffffff) + 1)
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def configure_session(port):
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# Native Espressif/Seeed/Adafruit USB and a CH340 bridge differ in DTR semantics.
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# Native Espressif/Seeed/Adafruit USB and CP2102/CH340 bridges differ in DTR semantics.
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# DTR keeps the native session active; on a bridge it can drive BOOT/GPIO0.
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port.rts = False
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port.dtr = any(info.vid in (0x303A, 0x2886, 0x239A) and info.device.casefold() == str(port.port).casefold()
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device = os.path.realpath(str(port.port)).casefold()
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port.dtr = any(info.vid in (0x303A, 0x2886, 0x239A)
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and os.path.realpath(str(info.device)).casefold() == device
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for info in list_ports.comports())
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@@ -1,5 +1,7 @@
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"""Regression tests for the serial HIL result reader."""
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import unittest
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from pathlib import Path
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from tempfile import TemporaryDirectory
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from unittest.mock import patch
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from types import SimpleNamespace
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from profile_switch import read_response, exchange_ready, configure_session, exchange
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@@ -19,6 +21,19 @@ class Port:
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return next(self.parts)
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class SessionPort:
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def __init__(self, device):
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self.port = device
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self.is_open = False
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self.dtr = True
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self.rts = True
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self.opened_control_lines = None
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def open(self):
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self.opened_control_lines = (self.dtr, self.rts)
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self.is_open = True
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class ResultReaderTests(unittest.TestCase):
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def test_timing_runs_get_correlated_cached_replies(self):
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port = Port([])
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@@ -29,15 +44,43 @@ class ResultReaderTests(unittest.TestCase):
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self.assertTrue(result["transport_recovered"])
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def test_native_usb_and_bridge_have_distinct_control_lines(self):
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for vid, expected in ((0x303A, True), (0x2886, True), (0x239A, True), (0x1A86, False), (None, False)):
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port = Port([])
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for vid, expected in ((0x303A, True), (0x2886, True), (0x239A, True),
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(0x1A86, False), (0x10C4, False), (None, False)):
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port = SessionPort("test")
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with patch("profile_switch.list_ports.comports", return_value=[
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SimpleNamespace(device="TEST", vid=vid),
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SimpleNamespace(device="different", vid=0x303A)]):
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configure_session(port)
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self.assertFalse(port.is_open)
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port.open()
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self.assertEqual(port.opened_control_lines, (expected, False))
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self.assertEqual(port.dtr, expected)
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self.assertFalse(port.rts)
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def test_by_id_symlinks_select_the_actual_native_or_cp2102_device(self):
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with TemporaryDirectory() as directory:
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root = Path(directory)
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native = root / "ttyACM0"
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bridge = root / "ttyUSB0"
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native.touch()
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bridge.touch()
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by_id = root / "serial" / "by-id"
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by_id.mkdir(parents=True)
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native_id = by_id / "usb-Espressif_USB_JTAG-if00"
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bridge_id = by_id / "usb-Silicon_Labs_CP2102-if00-port0"
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native_id.symlink_to(native)
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bridge_id.symlink_to(bridge)
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inventory = [SimpleNamespace(device=str(native), vid=0x303A),
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SimpleNamespace(device=str(bridge), vid=0x10C4)]
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for device, expected in ((native_id, True), (bridge_id, False)):
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with self.subTest(device=device.name):
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port = SessionPort(str(device))
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with patch("profile_switch.list_ports.comports", return_value=inventory):
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configure_session(port)
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self.assertFalse(port.is_open)
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port.open()
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self.assertEqual(port.opened_control_lines, (expected, False))
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def test_timeout_replays_cached_result_without_repeating_tx(self):
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port = Port([])
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with patch("profile_switch.read_response", side_effect=[
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