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https://github.com/liquidraver/ZephCore.git
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xiao_nrf54l15: catalog tile, verify board against schematics
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liquidraver
@@ -95,6 +95,7 @@ MAKER_BY_DEVICE = {
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"RAK6421 WisMesh (Raspberry Pi 5)": "rak",
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"muzi works R1 Neo": "muziworks",
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"MinewSemi ME25LS02": "minewsemi",
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"Seeed Studio Xiao nRF54L15": "seeed",
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}
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DESCRIPTION = (
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@@ -211,6 +212,10 @@ BOARDS = [
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# the .hex as a plain download and the user flashes it over SWD.
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dict(stem="me25ls02-nrf54l15-cpuapp", kind="nrf54l", device="MinewSemi ME25LS02",
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new=True, img="lora.svg"),
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# Same story, except the XIAO carries a SAMD11 CMSIS-DAP bridge, so its own
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# USB cable is enough (openocd/pyocd) -- still not a browser flash flow.
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dict(stem="xiao_nrf54l15-nrf54l15-cpuapp", kind="nrf54l",
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device="Seeed Studio Xiao nRF54L15", new=True, img="lora.svg"),
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# --- Native Linux (noflash, download only): new tiles ----------------
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dict(stem="zephcore_linux_femtofox", kind="linux", device="Femtofox (Luckfox Pico Mini)", new=True, img="lora.svg"),
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@@ -245,6 +245,11 @@ Proposed by **bisbille** ([@bisbille](https://github.com/bisbille)) —
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Housekeeping, listed for completeness — nothing here changes how a node behaves day to day.
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- **The XIAO nRF54L15 now ships firmware with every release.** The board has been supported for a
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while but was never part of the published build, so it had to be compiled by hand. Companion and
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repeater images are now built and listed alongside every other board. Like the ME25LS02 it is a
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`.hex` flashed over SWD — though the XIAO's own USB cable is enough, since it has a debug bridge
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built into the board.
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- **The Zephyr operating system underneath was updated** to a newer snapshot, and our radio patches were
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reorganised on top of it: five separate SX126x patches are now one. Same behaviour, fewer things to go
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wrong the next time Zephyr moves.
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@@ -117,10 +117,14 @@
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pinctrl-names = "default", "sleep";
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/*
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* The nRF54L SPIM applies an RX sample delay that the SX126x does not
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* tolerate at these clock rates — MinewSemi drop it in their own sample
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* and so do we. Symptom if left in: garbage on MISO, driver never sees
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* the chip.
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* MinewSemi delete the SoC's spi00 RX sample delay in their own working
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* sample, so we do the same rather than diverge from the one
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* configuration known to run on this module.
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*
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* Worth knowing: xiao_nrf54l15 is the same SoC driving the same radio at
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* the same 8 MHz and keeps rx-delay = 1, so this is not a rule about the
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* SoC — it is untested either way and each board keeps what its vendor
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* shipped. If someone ever A/B's it on hardware, unify the two.
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*/
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/delete-property/ rx-delay-supported;
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/delete-property/ rx-delay;
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@@ -139,6 +143,12 @@
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/* Crystal, not TCXO — do not add dio3-tcxo-voltage. */
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/*
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* The module fits the SX1262's DC-DC inductor (L7 on DCC_SW), and
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* the driver defaults to DC-DC regulator mode, so `regulator-ldo`
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* must NOT be added here — it would force the lossier LDO path.
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*/
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rx-boosted;
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};
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};
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@@ -2,16 +2,45 @@
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* SPDX-License-Identifier: MIT
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* XIAO nRF54L15 + Wio-SX1262 LoRa
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*
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* Verified 2026-08-22 against primary sources (see datasheets/README.md):
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* Seeed XIAO nRF54L15 schematic, the Wio-SX1262-for-XIAO carrier schematic,
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* and the Wio-SX1262-N module datasheet.
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*
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* Pin mapping (XIAO nRF54L15 connector → Wio-SX1262):
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* - D1 (P1.05) = DIO1 - D8 (P2.01) = SPI SCK (spi00)
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* - D2 (P1.06) = RESET - D9 (P2.04) = SPI MISO (spi00)
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* - D3 (P1.07) = BUSY - D10 (P2.02) = SPI MOSI (spi00)
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* - D4 (P1.10) = NSS
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* - D5 (P1.11) = RXEN
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* The D-pin numbers come from the XIAO schematic's connector sheet, and the
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* same D-pin assignment is used by our xiao_esp32c6 board on this same
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* Wio-SX1262 carrier — two independent boards agreeing on the kit's wiring.
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*
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* Radio module facts, from the Wio-SX1262-N module datasheet:
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* - RF_SW pin: "logic high level means enable receiver mode" → rx-enable-gpios
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* is active high, which is what is set below.
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* - DIO2 is internally connected to the RF switch, "logic high = enable
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* transmitter" → dio2-tx-enable, no separate TXEN line.
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* - DIO3 supplies the module's TCXO. Permitted 1.7–3.3 V, and it must stay at
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* least 200 mV below VCC (3.3 V here), so the 1.8 V below is in range.
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* - The module wires the SX1262 for DC-DC, not LDO. The Zephyr driver already
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* defaults to DC-DC — `regulator-ldo` must NOT be added to the lora node.
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*
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* Clocks: the XIAO carries its own 32.768 kHz crystal (7 pF, 20 ppm), so the
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* upstream board DTS enables LFXO and this node keeps accurate time. The
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* ME25LS02, the other nRF54L board here, has no such crystal and runs the RC
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* instead — do not copy clock settings between the two.
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*
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* Console: UART20 (P1.09 TX, P1.08 RX) via SAMD11 CMSIS-DAP bridge → USB CDC
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* Flash: RRAM (not traditional NV flash)
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* Flash via: SWD through SAMD11 CMSIS-DAP (west flash / openocd)
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* Flash via: SWD through SAMD11 CMSIS-DAP (west flash / openocd). The
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* nRF54L15 has no USB peripheral, so there is no UF2 or DFU path — the
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* published artifact is zephyr.hex, which links at RRAM base 0x0.
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*
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* Battery: the board has a charger (SGM40567, 200 mA) and a 2:1 divider on
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* P1.14/AIN7, gated by P1.15/VBAT_EN (already a boot-on regulator in the
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* upstream DTS). ZephCore does not read it yet — see the commented block at
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* the bottom of this file for what is known and what still has to be measured.
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*/
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#include <zephyr/dt-bindings/lora/sx126x.h>
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@@ -27,7 +56,16 @@
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status = "disabled";
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};
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/* SX1262 on spi00 (XIAO SPI bus — SCK/MISO/MOSI already in pinctrl) */
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/*
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* SX1262 on spi00 (XIAO SPI bus — SCK/MISO/MOSI already in pinctrl).
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*
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* Note the divergence from the ME25LS02, which is the same SoC talking to the
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* same radio: that board deletes `rx-delay-supported`/`rx-delay` from spi00
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* because MinewSemi's working sample does. This board keeps the SoC defaults
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* (rx-delay = 1) and works. Neither setting has been A/B'd on hardware, so
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* they are deliberately left as each board's known-good configuration rather
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* than unified on a guess.
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*/
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&spi00 {
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cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* D4 = P1.10 NSS */
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@@ -89,3 +127,49 @@
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/* LittleFS auto-mount — standard /lfs mount point */
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#include "../../common/filesystem.dtsi"
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/*
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* Battery voltage — NOT enabled, deliberately.
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*
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* The hardware is there: the schematic shows a 2:1 divider feeding P1.14/AIN7
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* ("battery voltage = ADC sampling voltage * 2.0"), enabled by P1.15/VBAT_EN,
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* which the upstream board DTS already declares as `vbat_pwr` with
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* regulator-boot-on. So a plain ADC read needs no extra power sequencing.
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*
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* What is missing is a trustworthy scale factor. ZephyrBoard computes
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* `mV = raw * vbat-mv-multiplier / 4096`, so the multiplier has to encode the
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* ADC's full-scale voltage, and the nRF54L15 SAADC is not the nRF52 part we
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* have that number for: its internal reference is 0.9 V, not 0.6 V, and DS
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* v1.0 §8.18.7 states the single-ended range as "± 0.5*VREF/GAIN" while the
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* saturation condition two lines later implies a full span of VREF/GAIN. Those
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* two readings differ by a factor of two — and getting it wrong by 2x means a
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* healthy pack reports as flat and the node warns about a battery that is fine.
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*
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* To finish this, measure it: enable the block below on a board with a known
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* cell voltage, read `raw`, and solve for the multiplier. With gain 1/4 and the
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* 0.9 V reference the full scale is either 3.6 V (multiplier 7200 for the 2:1
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* divider) or 1.8 V (multiplier 3600). One measurement settles it.
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*
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* &adc {
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* status = "okay";
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*
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* #address-cells = <1>;
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* #size-cells = <0>;
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*
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* channel@7 {
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* reg = <7>;
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* zephyr,gain = "ADC_GAIN_1_4";
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* zephyr,reference = "ADC_REF_INTERNAL";
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* zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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* zephyr,input-positive = <NRF_SAADC_AIN7>;
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* zephyr,resolution = <12>;
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* };
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* };
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*
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* / {
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* zephyr,user {
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* io-channels = <&adc 7>;
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* vbat-mv-multiplier = <7200>;
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* };
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* };
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*/
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