t3s3 fixes

README.md

@@ -46,6 +46,7 @@ Other benefits:
 | **XIAO ESP32-S3** | ESP32-S3 | SX1262 | BLE 5.0, 8MB flash, 8MB PSRAM |
 | **Station G2** | ESP32-S3 | SX1262 + PA (~20 dB gain) | OLED (SH1106), GPS, 16MB flash, 8MB PSRAM |
 | **LilyGo TLoRa C6** | ESP32-C6 | SX1262 | BLE 5.0, Wi-Fi 6 |
+| **LilyGo T3S3** | ESP32-S3 | SX1262 | OLED (SSD1306), button, TX LED, battery ADC, 4MB flash, 2MB PSRAM. **SX1262 variant only** — the SX1276/SX1280/LR1121 versions of this board are not supported |
 | **Heltec V3** | ESP32-S3 | SX1262 | OLED (SSD1306), 8MB flash |
 | **Heltec V4.2** | ESP32-S3 | SX1262 + GC1109 PA | OLED (SSD1306), 16MB flash, 2MB PSRAM |
 | **Heltec V4.3** | ESP32-S3 | SX1262 + KCT8103L PA | OLED (SSD1306), 16MB flash, 2MB PSRAM |

build.sh

@@ -40,6 +40,7 @@ ESP32_boards=(
     xiao_esp32c6/esp32c6/hpcore
     xiao_esp32s3/esp32s3/procpu
     lilygo_tlora_c6/esp32c6/hpcore
+    lilygo_t3s3/esp32s3/procpu
     station_g2/esp32s3/procpu
     heltec_wifi_lora32_v3/esp32s3/procpu
     heltec_wifi_lora32_v4/esp32s3/procpu

gen_provider_catalog.py

@@ -78,6 +78,7 @@ MAKER_BY_DEVICE = {
     "LilyGo T-Beam (SX1262)": "lilygo",
     "LilyGo T-Impulse Plus": "lilygo",
     "LilyGo T-Lora C6": "lilygo",
+    "LilyGo T3 S3 (SX126x)": "lilygo",
     "ProMicro nrf52 (faketec)": "promicro",
     "Heltec T114": "heltec",
     "Heltec Mesh Node T096": "heltec",
@@ -185,6 +186,10 @@ BOARDS = [
     dict(stem="heltec_wifi_lora32_v4-esp32s3-procpu", kind="esp32", device="Heltec v4"),
     dict(stem="heltec_wireless_tracker-esp32s3-procpu",    kind="esp32", device="Heltec Wireless Tracker"),
     dict(stem="heltec_wireless_tracker_v2-esp32s3-procpu", kind="esp32", device="Heltec Wireless Tracker v2"),
+    # MeshCore splits this board by radio -- "(SX126x)" and "(SX127x)" are two
+    # separate tiles sharing the "LilyGo T3 S3" group. We only build the SX1262
+    # variant, so fold into the SX126x tile; an SX127x port would be its own entry.
+    dict(stem="lilygo_t3s3-esp32s3-procpu",        kind="esp32", device="LilyGo T3 S3 (SX126x)"),
     # ThinkNode M9 pulled from the build.sh release matrix 2026-07-22 (bring-up
     # still in progress — keypad/GPS/battery unverified on hardware). Restore
     # this line together with the build.sh entry once it's release-ready.

zephcore/CMakeLists.txt

@@ -385,7 +385,9 @@ endif()
 # so both the packet wake and the console flush land correctly. Deliberately
 # ABSENT and must stay absent unless their wiring changes:
 #   xiao_esp32s3 (DIO1=GPIO39), station_g2 (GPIO48), thinknode_m9 (GPIO42),
-#   lilygo_tlora_c6 (GPIO23, outside the C6's LP range 0-7)
+#   lilygo_tlora_c6 (GPIO23, outside the C6's LP range 0-7),
+#   lilygo_t3s3 (GPIO33 — and its console is USB Serial/JTAG, so it fails
+#     the second test below as well)
 #     -> cannot wake on a received packet; the node would go deaf while
 #        looking excellent on a current meter.
 #   ttgo_lora32 -> SX127x; patches/zephyr/0012 arms DIO1 in the sx126x driver

zephcore/boards/esp32/lilygo_t3s3/Kconfig

@@ -2,4 +2,4 @@
 # allocations on top of the esp32_common.conf platform heap.
 config HEAP_MEM_POOL_ADD_SIZE_BOARD
 	int
-	default 4096
+	default 4096

zephcore/boards/esp32/lilygo_t3s3/Kconfig.lilygo_t3s3

@@ -1,3 +1,7 @@
+# LilyGo T3S3 board configuration
+
+# SPDX-License-Identifier: MIT
+
 config BOARD_LILYGO_T3S3
 	select SOC_ESP32S3_WROOM_N4R2
-	select SOC_ESP32S3_PROCPU if BOARD_LILYGO_T3S3_ESP32S3_PROCPU
+	select SOC_ESP32S3_PROCPU if BOARD_LILYGO_T3S3_ESP32S3_PROCPU

zephcore/boards/esp32/lilygo_t3s3/board.cmake

@@ -1,7 +1,9 @@
+# SPDX-License-Identifier: MIT
+
 if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
   set(OPENOCD OPENOCD-NOTFOUND)
 endif()
 find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
 
 include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
-include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

zephcore/boards/esp32/lilygo_t3s3/board.conf

@@ -9,10 +9,17 @@
 #
 # Include order: prj.conf → zephcore_common.conf → esp32_common.conf → board.conf
 
-# Board identification
-CONFIG_ZEPHCORE_BOARD_NAME="LilyGo T3S3"
-CONFIG_BT_DIS_MODEL_NUMBER_STR="LilyGo T3S3"
+# Board identification.
+#
+# The T3S3 ships with several different radios (SX1262, SX1276, SX1280, LR1121)
+# behind one product name. Upstream MeshCore splits it into LilyGo_T3S3_sx1262
+# and LilyGo_T3S3_sx1276 envs, and the Mesh America configurator carries two
+# separate tiles, "LilyGo T3 S3 (SX126x)" and "(SX127x)". Only the SX1262
+# variant is supported here, so the radio is part of the name: flashing this to
+# an SX1276 board yields a silent radio rather than an obvious failure.
+CONFIG_ZEPHCORE_BOARD_NAME="LilyGo T3S3 (SX1262)"
+CONFIG_BT_DIS_MODEL_NUMBER_STR="LilyGo T3S3 (SX1262)"
 
 # SX1262 — 22 dBm TX power (MeshCore variant default)
 CONFIG_ZEPHCORE_DEFAULT_TX_POWER_DBM=22
-CONFIG_ZEPHCORE_MAX_TX_POWER_DBM=22
+CONFIG_ZEPHCORE_MAX_TX_POWER_DBM=22

zephcore/boards/esp32/lilygo_t3s3/board.overlay

@@ -167,4 +167,4 @@
  * boards/common/esp32s3_usb.overlay and applies only when that conf is passed.
  * Do NOT include esp32s3_console_uart0.dtsi here: it would move the console
  * onto GPIO43/44 in every build of this board. */
-#include "../../common/esp32s3_usb_otg.dtsi"
+#include "../../common/esp32s3_usb_otg.dtsi"

zephcore/boards/esp32/lilygo_t3s3/board.yml

@@ -1,6 +1,8 @@
+# SPDX-License-Identifier: MIT
+
 board:
   name: lilygo_t3s3
   full_name: LilyGo T3S3
   vendor: lilygo
   socs:
-    - name: esp32s3
+    - name: esp32s3

zephcore/boards/esp32/lilygo_t3s3/lilygo_t3s3-pinctrl.dtsi

@@ -39,4 +39,4 @@
 			output-high;
 		};
 	};
-};
+};

zephcore/boards/esp32/lilygo_t3s3/lilygo_t3s3_procpu.dts

@@ -20,7 +20,16 @@
 
 #include <espressif/esp32s3/esp32s3_wroom_n4r2.dtsi>
 #include "lilygo_t3s3-pinctrl.dtsi"
-#include <espressif/partitions_0x0_amp_4M.dtsi>
+/*
+ * Base flash map: the *default* 4M table, not the _amp_ variant.
+ * partitions.overlay reclaims the stock layout with a /delete-node/ list whose
+ * labels match this table exactly. The amp table additionally defines
+ * slot0_appcpu (0x2C0000) and slot1_appcpu (0x330000..0x3A0000), which that
+ * list does not delete — they would survive and overlap the new slot1
+ * (0x1D6000..0x39C000) and storage (0x39C000). This board builds procpu-only,
+ * so the appcpu slots serve no purpose here in any case.
+ */
+#include <espressif/partitions_0x0_default_4M.dtsi>
 
 / {
 	model = "LilyGo T3S3";
@@ -78,4 +87,4 @@
 
 &wifi {
 	status = "okay";
-};
+};

zephcore/boards/esp32/lilygo_t3s3/lilygo_t3s3_procpu_defconfig

@@ -9,4 +9,4 @@ CONFIG_SPI=y
 CONFIG_I2C=y
 CONFIG_FLASH=y
 CONFIG_FLASH_MAP=y
-CONFIG_NVS=y
+CONFIG_NVS=y

zephcore/boards/esp32/lilygo_t3s3/partitions.overlay

@@ -7,9 +7,14 @@
  * address than the app writes it to and OTA silently reverts on reboot.
  *
  * slot0 starts at 0x10000 (right after the 64KB MCUboot region), matching the
- * Arduino/ESP-IDF app offset (Mesh America "flash-update" compatible). sys_partition
- * is reclaimed. Slots are equal size and slot1 ends exactly on the unchanged
- * storage/lfs offsets, so a -merged reflash keeps identity/prefs/contacts/BLE-bonds.
+ * Arduino/ESP-IDF app offset (Mesh America "flash-update" compatible). The stock
+ * sys / lpcore / scratch / coredump partitions are reclaimed. The two app slots
+ * are equal size and end exactly where storage and lfs begin, so a -merged
+ * reflash rewrites only MCUboot + slot0 and leaves identity, prefs, contacts and
+ * BLE bonds intact.
+ *
+ * Nothing here is inherited: the base table is partitions_0x0_default_4M.dtsi
+ * (see the DTS) and every label below is deleted and redefined.
  *
  * 4MB layout.
  */
@@ -30,7 +35,8 @@
 
 &flash0 {
 	partitions {
-		/* App slots — equal size (swap-mode compatible), slot0 at 0x10000. */
+		/* App slots — slot0 at 0x10000. sysbuild.conf selects MCUboot
+		 * OVERWRITE_ONLY, but keeping them equal size leaves swap available. */
 		slot0_partition: partition@10000 {
 			label = "image-0";
 			reg = <0x10000 0x1C6000>;
@@ -39,15 +45,15 @@
 			label = "image-1";
 			reg = <0x1D6000 0x1C6000>;
 		};
-		/* BLE bond NVS — offset unchanged so bonds survive the reflash. */
+		/* BLE bond NVS — above slot1, so bonds survive a -merged reflash. */
 		storage_partition: partition@39C000 {
 			label = "storage";
 			reg = <0x39C000 0x4000>;
 		};
-		/* LittleFS (identity/prefs/contacts) — offset unchanged. */
+		/* LittleFS (identity/prefs/contacts) — above slot1, same reason. */
 		lfs_partition: partition@3A0000 {
 			label = "lfs";
 			reg = <0x3A0000 0x60000>;
 		};
 	};
-};
+};

zephcore/boards/example_board/README.md

@@ -41,6 +41,7 @@ SWD flash: `west flash` (requires J-Link, pyocd, or nrfjprog connected).
 | XIAO ESP32-C3        | `west build -b xiao_esp32c3 zephcore`                   | `west flash`    |
 | XIAO ESP32-C6        | `west build -b xiao_esp32c6/esp32c6/hpcore zephcore`    | `west flash`    |
 | LilyGo TLoRa C6      | `west build -b lilygo_tlora_c6/esp32c6/hpcore zephcore` | `west flash`    |
+| LilyGo T3S3 (SX1262) | `west build -b lilygo_t3s3/esp32s3/procpu zephcore`     | `west flash`    |
 | XIAO ESP32-S3        | `west build -b xiao_esp32s3/esp32s3/procpu zephcore`     | `west flash`    |
 | Station G2           | `west build -b station_g2/esp32s3/procpu zephcore`       | `west flash`    |
 | Heltec V3            | `west build -b heltec_wifi_lora32_v3/esp32s3/procpu zephcore` | `west flash` |