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add tlorac6, switch of asserts in all esp

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liquidraver
2026-02-23 13:50:57 +01:00
parent f3afb6433d
commit 37d2b777d7
11 changed files with 275 additions and 4 deletions
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zephcore/CMakeLists.txt
+1 -1
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@@ -187,7 +187,7 @@ if(BOARD MATCHES ".*nrf52.*" OR BOARD MATCHES "rak4631" OR BOARD MATCHES "wio_tr
set(ZEPHCORE_PLATFORM_CONF "${CMAKE_CURRENT_SOURCE_DIR}/boards/common/nrf52_common.conf")
elseif(DEFINED BOARD_QUALIFIERS AND BOARD_QUALIFIERS MATCHES ".*nrf52.*")
set(ZEPHCORE_PLATFORM_CONF "${CMAKE_CURRENT_SOURCE_DIR}/boards/common/nrf52_common.conf")
elseif(BOARD MATCHES ".*esp32.*" OR BOARD MATCHES "station_g2")
elseif(BOARD MATCHES ".*esp32.*" OR BOARD MATCHES "station_g2" OR BOARD MATCHES "lilygo_tlora_c6")
set(ZEPHCORE_PLATFORM_CONF "${CMAKE_CURRENT_SOURCE_DIR}/boards/common/esp32_common.conf")
elseif(DEFINED BOARD_QUALIFIERS AND BOARD_QUALIFIERS MATCHES ".*esp32.*")
set(ZEPHCORE_PLATFORM_CONF "${CMAKE_CURRENT_SOURCE_DIR}/boards/common/esp32_common.conf")
zephcore/boards/common/esp32_common.conf
+6 -3
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@@ -16,6 +16,9 @@ CONFIG_BT_TX_PROCESSOR_STACK_SIZE=2048
CONFIG_HEAP_MEM_POOL_SIZE=32768
# ========== Debug ==========
# Generic Zephyr assert (ESP32 uses Espressif BLE blob, not sw_split controller,
# so BT_CTLR_ASSERT_HANDLER is not available)
CONFIG_ASSERT=y
# CONFIG_ASSERT disabled for ESP32: Espressif's closed-source BLE controller
# blob leaves IRQs in a state that triggers false "Context switching while
# holding lock!" assertions in kswap.h. The BLE stack works correctly — the
# blob manages its own IRQ state internally. nRF52/nRF54L boards keep asserts
# via their platform configs; ESP32 relies on logging for debug.
# CONFIG_ASSERT=n (Zephyr default)
zephcore/boards/esp32/lilygo_tlora_c6/Kconfig
+3
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@@ -0,0 +1,3 @@
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 4096
zephcore/boards/esp32/lilygo_tlora_c6/Kconfig.lilygo_tlora_c6
+7
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@@ -0,0 +1,7 @@
# LilyGo T-LoRa C6 board configuration
# SPDX-License-Identifier: Apache-2.0
config BOARD_LILYGO_TLORA_C6
select SOC_ESP32_C6_WROOM_1U_N4
select SOC_ESP32C6_HPCORE if BOARD_LILYGO_TLORA_C6_ESP32C6_HPCORE
zephcore/boards/esp32/lilygo_tlora_c6/board.cmake
+9
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@@ -0,0 +1,9 @@
# SPDX-License-Identifier: Apache-2.0
if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
set(OPENOCD OPENOCD-NOTFOUND)
endif()
find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
zephcore/boards/esp32/lilygo_tlora_c6/board.conf
+22
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@@ -0,0 +1,22 @@
# SPDX-License-Identifier: Apache-2.0
# LilyGo T-LoRa C6 (T3-C6) + SX1262 LoRa
#
# Hardware:
# - ESP32-C6-MINI-1U (RISC-V, 4MB flash, BLE 5.0, Wi-Fi 6)
# - SX1262 LoRa on SPI2: NSS=GPIO18, DIO1=GPIO23, BUSY=GPIO22,
# RESET=GPIO21, RXEN=GPIO15, TXEN=GPIO14
# - TCXO 1.8V, DIO2 as RF switch, RX boosted
# - User LED on GPIO7 (active HIGH)
# - USB-Serial/JTAG for console
# Board identification
CONFIG_ZEPHCORE_BOARD_NAME="LilyGo TLoRa C6"
# Device Information Service model name
CONFIG_BT_DIS_MODEL_NUMBER_STR="LilyGo TLoRa C6"
# Radio type
CONFIG_ZEPHCORE_RADIO_NATIVE=y
# Flash size (T3-C6 has 4MB, override Zephyr default)
CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
zephcore/boards/esp32/lilygo_tlora_c6/board.overlay
+92
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@@ -0,0 +1,92 @@
/*
* SPDX-License-Identifier: Apache-2.0
* LilyGo T-LoRa C6 (T3-C6) + SX1262 LoRa
*
* Pin mapping (from Arduino MeshCore variants/lilygo_tlora_c6):
* SPI: SCLK=GPIO6, MISO=GPIO1, MOSI=GPIO0, NSS=GPIO18
* LoRa: DIO1=GPIO23, BUSY=GPIO22, RESET=GPIO21
* RF: RXEN=GPIO15, TXEN=GPIO14, DIO2 as RF switch
* I2C: SDA=GPIO8, SCL=GPIO9
* LED: GPIO7 (active HIGH)
*
* Console: USB-Serial/JTAG (usb_serial)
*/
/ {
aliases {
lora0 = &lora;
led0 = &user_led;
};
chosen {
zephyr,settings-partition = &storage_partition;
};
leds {
compatible = "gpio-leds";
user_led: led_0 {
gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
label = "User LED";
};
};
};
/* SX1262 on SPI2 */
&spi2 {
cs-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; /* GPIO18 NSS */
lora: lora@0 {
compatible = "semtech,sx1262";
reg = <0>;
spi-max-frequency = <8000000>;
/* LoRa control pins */
reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; /* GPIO21 */
busy-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; /* GPIO22 */
dio1-gpios = <&gpio0 23 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; /* GPIO23 */
/* RF switch: RXEN + TXEN GPIOs, plus DIO2 as RF switch */
rx-enable-gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* GPIO15 RXEN */
tx-enable-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* GPIO14 TXEN */
dio2-tx-enable;
/* TCXO 1.8V via DIO3 */
dio3-tcxo-voltage = <2>;
tcxo-power-startup-delay-ms = <10>;
/* RX boosted mode for better sensitivity */
rx-boosted;
};
};
/*
* Flash partitions — split default storage into NVS + LittleFS.
* Standard ESP32 4MB layout:
* 0x3B0000 - 0x3B2000 (8KB) NVS (BLE bonds)
* 0x3B2000 - 0x3E0000 (184KB) LittleFS (identity, contacts)
*/
/delete-node/ &storage_partition;
&flash0 {
partitions {
/* NVS 8KB for BLE bonds + settings */
storage_partition: partition@3b0000 {
label = "storage";
reg = <0x3B0000 0x2000>;
};
/* LittleFS 184KB for DataStore */
lfs_partition: partition@3b2000 {
label = "lfs";
reg = <0x3B2000 0x2E000>;
};
};
};
/* LittleFS auto-mount — standard /lfs mount point */
#include "../../common/filesystem.dtsi"
/* WiFi — required for OTA firmware updates */
&wifi {
status = "okay";
};
zephcore/boards/esp32/lilygo_tlora_c6/board.yml
+6
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@@ -0,0 +1,6 @@
board:
name: lilygo_tlora_c6
full_name: LilyGo T-LoRa C6
vendor: lilygo
socs:
- name: esp32c6
zephcore/boards/esp32/lilygo_tlora_c6/lilygo_tlora_c6-pinctrl.dtsi
+38
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@@ -0,0 +1,38 @@
/*
* SPDX-License-Identifier: Apache-2.0
* LilyGo T-LoRa C6 — Pin Control Definitions
*
* Pin mapping (from Arduino MeshCore variants/lilygo_tlora_c6):
* LoRa SPI2: SCLK=GPIO6, MOSI=GPIO0, MISO=GPIO1, NSS=GPIO18
* I2C0: SDA=GPIO8, SCL=GPIO9
* Console: USB-Serial/JTAG (built-in)
*/
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
#include <zephyr/dt-bindings/pinctrl/esp32c6-pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/esp32c6-gpio-sigmap.h>
&pinctrl {
/* SPI2 — LoRa SX1262 (CS handled via cs-gpios, not pinctrl) */
spim2_default: spim2_default {
group1 {
pinmux = <SPIM2_MISO_GPIO1>,
<SPIM2_SCLK_GPIO6>;
};
group2 {
pinmux = <SPIM2_MOSI_GPIO0>;
output-low;
};
};
/* I2C0 — expansion header (sensors, etc.) */
i2c0_default: i2c0_default {
group1 {
pinmux = <I2C0_SDA_GPIO8>,
<I2C0_SCL_GPIO9>;
bias-pull-up;
drive-open-drain;
output-high;
};
};
};
zephcore/boards/esp32/lilygo_tlora_c6/lilygo_tlora_c6_hpcore.dts
+79
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@@ -0,0 +1,79 @@
/*
* SPDX-License-Identifier: Apache-2.0
* LilyGo T-LoRa C6 (T3-C6) — ESP32-C6-MINI-1U, 4MB flash
*
* Hardware:
* MCU: ESP32-C6 (RISC-V single-core, BLE 5.0, Wi-Fi 6, 802.15.4)
* Flash: 4 MB
* Radio: SX1262 LoRa on SPI2
* LED: GPIO7 (active HIGH)
* Console: USB-Serial/JTAG (built-in)
*/
/dts-v1/;
#include <espressif/esp32c6/esp32c6_wroom_n4.dtsi>
#include "lilygo_tlora_c6-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <espressif/partitions_0x0_default.dtsi>
/ {
model = "LilyGo T-LoRa C6";
compatible = "lilygo,tlora-c6";
chosen {
zephyr,sram = &sramhp;
zephyr,console = &usb_serial;
zephyr,shell-uart = &usb_serial;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,ieee802154 = &ieee802154;
};
aliases {
watchdog0 = &wdt0;
};
};
&usb_serial {
status = "okay";
};
&trng0 {
status = "okay";
};
&gpio0 {
status = "okay";
};
&wdt0 {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
};
&spi2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-0 = <&spim2_default>;
pinctrl-names = "default";
};
&wifi {
status = "okay";
};
&ieee802154 {
status = "okay";
};
&esp32_bt_hci {
status = "okay";
};
zephcore/boards/esp32/lilygo_tlora_c6/lilygo_tlora_c6_hpcore_defconfig
+12
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@@ -0,0 +1,12 @@
# LilyGo T-LoRa C6 — minimal Zephyr defconfig (hpcore)
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
CONFIG_CLOCK_CONTROL=y
CONFIG_PINCTRL=y
CONFIG_SPI=y
CONFIG_I2C=y
CONFIG_FLASH=y
CONFIG_FLASH_MAP=y
CONFIG_NVS=y