mirror of
https://github.com/liquidraver/ZephCore.git
synced 2026-09-01 23:08:19 +00:00
make formatter more universal
This commit is contained in:
liquidraver
@@ -57,4 +57,4 @@ message(STATUS "Formatter board conf: ${FMT_BOARD_CONF}")
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(zephcore_formatter)
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target_sources(app PRIVATE src/main.c)
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target_sources(app PRIVATE src/main.c src/qspi_probe.c)
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@@ -0,0 +1,4 @@
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# T1000-E formatter config — disable peripherals from board DTS
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CONFIG_GNSS=n
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CONFIG_I2C=n
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CONFIG_SENSOR=n
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@@ -0,0 +1,30 @@
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/*
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* T1000-E formatter overlay — USB console only.
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* Strips GPS/sensor nodes from the main board overlay
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* to avoid driver init hangs in the minimal formatter environment.
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*
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* This overlay is used as the SDv7 universal build target.
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* The resulting UF2 works on ALL nRF52840 boards with SoftDevice v7:
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* T1000-E, Wio Tracker L1, Ikoka Nano 30dBm
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*/
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/ {
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chosen {
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zephyr,console = &cdc_acm_uart;
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zephyr,shell-uart = &cdc_acm_uart;
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};
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/* Delete GPS control nodes from main board overlay */
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/delete-node/ gps-enable;
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/delete-node/ gps-vrtc-enable;
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/delete-node/ gps-reset;
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/delete-node/ gps-sleep-int;
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/delete-node/ gps-rtc-int;
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/delete-node/ gps-resetb;
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};
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&zephyr_udc0 {
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cdc_acm_uart: cdc_acm_uart {
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compatible = "zephyr,cdc-acm-uart";
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};
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};
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@@ -7,6 +7,4 @@ CONFIG_INPUT=n
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CONFIG_ADC=n
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CONFIG_REGULATOR=n
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# QSPI flash present — enable driver to erase /ext partition
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CONFIG_NORDIC_QSPI_NOR=y
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CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE=4096
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# QSPI erase now handled by bare-metal probe (qspi_probe.c) — no driver needed
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@@ -1,3 +1,2 @@
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# Wio Tracker L1 — QSPI flash present (P25Q16H 2MB)
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CONFIG_NORDIC_QSPI_NOR=y
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CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE=4096
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# Wio Tracker L1 formatter config
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# QSPI erase now handled by bare-metal probe (qspi_probe.c) — no driver needed
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@@ -1,5 +1,5 @@
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# ZephCore Flash Formatter — minimal config
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# Board-specific QSPI enablement comes from board.conf
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# ZephCore Universal Flash Formatter — minimal config
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# QSPI erase uses bare-metal register probing (qspi_probe.c) — no driver needed
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# Flash access
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CONFIG_FLASH=y
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@@ -4,16 +4,23 @@
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* Erases all filesystem partitions and reboots into Adafruit UF2 DFU mode
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* for clean firmware installation.
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*
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* All platforms use DTS FIXED_PARTITION_EXISTS guards — no hardcoded addresses.
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* nRF52 boards sharing the same SoftDevice version use the same partition dtsi,
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* so a single UF2 works on every board with that SoftDevice version.
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* QSPI is compile-time conditional — included only when building for a
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* QSPI-capable board target (pin config is board-specific).
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* Only TWO UF2 binaries are needed for all nRF52840 boards:
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* - SDv6: covers RAK4631, ThinkNode M1/M3/M6, ProMicro LR2021, RAK WisMesh Tag
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* - SDv7: covers T1000-E, Wio Tracker L1, Ikoka Nano 30dBm
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*
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* Internal flash uses DTS FIXED_PARTITION_EXISTS — partition layout is identical
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* across all boards with the same SoftDevice version.
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*
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* QSPI external flash uses bare-metal register probing (qspi_probe.c) — no
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* Zephyr QSPI driver needed. The probe table contains known pin configurations
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* for all QSPI-capable boards; it auto-detects which board is running and
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* erases the external flash if present, or silently skips if not.
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*
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* Build:
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* SD v7: west build -b t1000_e/nrf52840 zephcore/tools/formatter --pristine
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* SD v6: west build -b rak4631/nrf52840 zephcore/tools/formatter --pristine
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* SD v7 + QSPI: west build -b wio_tracker_l1/nrf52840 zephcore/tools/formatter --pristine
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* SDv6: west build -b rak4631/nrf52840 zephcore/tools/formatter --pristine
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* SDv7: west build -b t1000_e/nrf52840 zephcore/tools/formatter --pristine
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*
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* Flash: drag-drop build/zephyr/zephyr.uf2 onto UF2 drive
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -24,6 +31,7 @@
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/storage/flash_map.h>
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#include <zephyr/sys/reboot.h>
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#include "qspi_probe.h"
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#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF52)
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#include <hal/nrf_power.h>
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@@ -113,14 +121,8 @@ int main(void)
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}
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#endif
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/* ── QSPI external flash (boards with external QSPI) ── */
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#if FIXED_PARTITION_EXISTS(qspi_storage_partition)
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if (erase_partition(FIXED_PARTITION_ID(qspi_storage_partition), "QSPI external (/ext)")) {
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errors++;
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}
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#else
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printk(" QSPI: not present in build target — skipped\n");
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#endif
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/* ── QSPI external flash (auto-detect via pin probing) ── */
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qspi_probe_and_erase(); /* Probes all known boards; skips if no flash found */
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led_off();
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@@ -0,0 +1,344 @@
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/*
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* SPDX-License-Identifier: Apache-2.0
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* Universal QSPI flash probe and erase — bare-metal nRF52840 register access
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*
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* Bypasses the Zephyr QSPI driver entirely. Directly configures the nRF52840
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* QSPI peripheral's PSEL (pin select) registers, sends standard JEDEC SPI NOR
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* commands via the custom instruction interface (CINSTR), and performs a full
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* chip erase when a flash chip responds.
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*
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* To add a new board: append an entry to known_boards[] with its QSPI pin
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* mapping and optional power-enable GPIO. No DTS or Kconfig changes needed.
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*/
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#include <zephyr/kernel.h>
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#include "qspi_probe.h"
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#if defined(CONFIG_SOC_NRF52840)
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#include <nrfx.h>
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#include <hal/nrf_gpio.h>
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/* ── SPI NOR flash commands (JEDEC standard — all chips) ──── */
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#define CMD_READ_ID 0x9F /* Read JEDEC ID: manufacturer + type + capacity */
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#define CMD_WRITE_EN 0x06 /* Write Enable (required before erase) */
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#define CMD_CHIP_ERASE 0xC7 /* Full chip erase */
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#define CMD_READ_STATUS 0x05 /* Read Status Register 1 */
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#define STATUS_WIP 0x01 /* Write-In-Progress bit in status register */
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/* ── CINSTRCONF length values (opcode + N-1 data bytes) ───── */
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#define CINSTR_1B 1 /* opcode only */
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#define CINSTR_2B 2 /* opcode + 1 byte response */
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#define CINSTR_4B 4 /* opcode + 3 bytes response (JEDEC ID) */
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/* ── Pin encoding: matches nRF52840 PSEL register format ──── */
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#define QPIN(port, pin) (((port) << 5) | (pin))
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#define QPIN_NONE 0xFF
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#define QPIN_PORT(p) (((p) >> 5) & 1)
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#define QPIN_PIN(p) ((p) & 0x1F)
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/* PSEL register value: pin connected */
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#define PSEL_DISCONNECT (1UL << 31)
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/* ── Known board QSPI pin configurations ─────────────────── */
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struct qspi_pin_config {
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const char *name;
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uint8_t sck, csn, io0, io1, io2, io3;
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uint8_t pwr_pin; /* GPIO to drive HIGH before probe, QPIN_NONE if none */
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};
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/*
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* Pin table — add new boards here.
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* Sourced from ZephCore DTS + Arduino MeshCore variants.
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*
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* Config SCK CSN IO0 IO1 IO2 IO3 PWR Flash chip Boards
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* ───────────────────────── ──────── ──────── ──────── ──────── ──────── ──────── ──────── ──────────────── ────────────────────────────────────────
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* Wio/XIAO/Ikoka/SenseCap P0.21 P0.25 P0.20 P0.24 P0.22 P0.23 — P25Q16H 2MB Wio Tracker L1, XIAO nRF52, Ikoka Stick/Nano/Handheld, SenseCap Solar
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* ThinkNode M1 / TEcho P1.14 P1.15 P1.12 P1.13 P0.07 P0.05 — MX25R1635F 2MB ThinkNode M1, LilyGo TEcho
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* ThinkNode M6 P1.03 P0.23 P1.01 P1.02 P1.04 P1.05 P0.21 MX25R1635F 2MB ThinkNode M6
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* RAK4631 / GAT562 P0.03 P0.26 P0.30 P0.29 P0.28 P0.02 — IS25LP080D 1MB RAK4631, RAK3401, GAT562 variants
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* LilyGo TEcho Lite P0.04 P0.12 P0.06 P0.08 P1.09 P0.26 — ZD25WQ32C 4MB LilyGo TEcho Lite
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* Nano G2 Ultra P0.08 P1.07 P0.06 P0.26 P1.04 P1.02 — W25Q16JV 2MB Nano G2 Ultra
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*/
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static const struct qspi_pin_config known_boards[] = {
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{
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.name = "Wio/XIAO/Ikoka/SenseCap",
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.sck = QPIN(0, 21), .csn = QPIN(0, 25),
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.io0 = QPIN(0, 20), .io1 = QPIN(0, 24),
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.io2 = QPIN(0, 22), .io3 = QPIN(0, 23),
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.pwr_pin = QPIN_NONE,
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},
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{
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.name = "ThinkNode M1 / TEcho",
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.sck = QPIN(1, 14), .csn = QPIN(1, 15),
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.io0 = QPIN(1, 12), .io1 = QPIN(1, 13),
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.io2 = QPIN(0, 7), .io3 = QPIN(0, 5),
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.pwr_pin = QPIN_NONE,
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},
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{
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.name = "ThinkNode M6",
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.sck = QPIN(1, 3), .csn = QPIN(0, 23),
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.io0 = QPIN(1, 1), .io1 = QPIN(1, 2),
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.io2 = QPIN(1, 4), .io3 = QPIN(1, 5),
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.pwr_pin = QPIN(0, 21),
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},
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{
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.name = "RAK4631 / GAT562",
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.sck = QPIN(0, 3), .csn = QPIN(0, 26),
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.io0 = QPIN(0, 30), .io1 = QPIN(0, 29),
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.io2 = QPIN(0, 28), .io3 = QPIN(0, 2),
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.pwr_pin = QPIN_NONE,
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},
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{
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.name = "LilyGo TEcho Lite",
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.sck = QPIN(0, 4), .csn = QPIN(0, 12),
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.io0 = QPIN(0, 6), .io1 = QPIN(0, 8),
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.io2 = QPIN(1, 9), .io3 = QPIN(0, 26),
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.pwr_pin = QPIN_NONE,
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},
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{
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.name = "Nano G2 Ultra",
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.sck = QPIN(0, 8), .csn = QPIN(1, 7),
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.io0 = QPIN(0, 6), .io1 = QPIN(0, 26),
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.io2 = QPIN(1, 4), .io3 = QPIN(1, 2),
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.pwr_pin = QPIN_NONE,
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},
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};
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/* ── GPIO helpers (raw register access) ───────────────────── */
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static NRF_GPIO_Type *gpio_port_reg(uint8_t qpin)
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{
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return QPIN_PORT(qpin) ? NRF_P1 : NRF_P0;
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}
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static void gpio_set_output_high(uint8_t qpin)
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{
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NRF_GPIO_Type *port = gpio_port_reg(qpin);
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uint8_t pin = QPIN_PIN(qpin);
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nrf_gpio_cfg_output(qpin);
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port->OUTSET = (1UL << pin);
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}
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static void gpio_release(uint8_t qpin)
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{
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NRF_GPIO_Type *port = gpio_port_reg(qpin);
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uint8_t pin = QPIN_PIN(qpin);
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port->OUTCLR = (1UL << pin);
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nrf_gpio_cfg_default(qpin);
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}
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/* ── QSPI register helpers ────────────────────────────────── */
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static void qspi_disconnect_pins(void)
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{
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NRF_QSPI->PSEL.SCK = PSEL_DISCONNECT;
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NRF_QSPI->PSEL.CSN = PSEL_DISCONNECT;
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NRF_QSPI->PSEL.IO0 = PSEL_DISCONNECT;
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NRF_QSPI->PSEL.IO1 = PSEL_DISCONNECT;
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NRF_QSPI->PSEL.IO2 = PSEL_DISCONNECT;
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NRF_QSPI->PSEL.IO3 = PSEL_DISCONNECT;
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}
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static void qspi_set_pins(const struct qspi_pin_config *cfg)
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{
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NRF_QSPI->PSEL.SCK = cfg->sck;
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NRF_QSPI->PSEL.CSN = cfg->csn;
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||||
NRF_QSPI->PSEL.IO0 = cfg->io0;
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||||
NRF_QSPI->PSEL.IO1 = cfg->io1;
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NRF_QSPI->PSEL.IO2 = cfg->io2;
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NRF_QSPI->PSEL.IO3 = cfg->io3;
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}
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static bool qspi_wait_ready(int timeout_ms)
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{
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int64_t deadline = k_uptime_get() + timeout_ms;
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while (!NRF_QSPI->EVENTS_READY) {
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||||
if (k_uptime_get() > deadline) {
|
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return false;
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}
|
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k_msleep(1);
|
||||
}
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||||
NRF_QSPI->EVENTS_READY = 0;
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return true;
|
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}
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|
||||
static bool qspi_activate(void)
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{
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||||
/* Single-bit SPI mode, 24-bit addressing, no DPM */
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||||
NRF_QSPI->IFCONFIG0 = 0;
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|
||||
/* 2 MHz (SCKFREQ=15 → 32MHz/16), 8µs CSN delay, SPI mode 0 */
|
||||
NRF_QSPI->IFCONFIG1 = (15UL << 28) | 128;
|
||||
|
||||
NRF_QSPI->ENABLE = QSPI_ENABLE_ENABLE_Enabled;
|
||||
NRF_QSPI->EVENTS_READY = 0;
|
||||
NRF_QSPI->TASKS_ACTIVATE = 1;
|
||||
|
||||
return qspi_wait_ready(500);
|
||||
}
|
||||
|
||||
static void qspi_deactivate(void)
|
||||
{
|
||||
NRF_QSPI->EVENTS_READY = 0;
|
||||
NRF_QSPI->TASKS_DEACTIVATE = 1;
|
||||
qspi_wait_ready(500);
|
||||
NRF_QSPI->ENABLE = QSPI_ENABLE_ENABLE_Disabled;
|
||||
qspi_disconnect_pins();
|
||||
}
|
||||
|
||||
/**
|
||||
* Execute a custom instruction via CINSTR interface.
|
||||
* @param opcode SPI NOR command opcode
|
||||
* @param len Total bytes (opcode + response), 1-9
|
||||
* @param dat0 Output: CINSTRDAT0 register value (response bytes), or NULL
|
||||
* @return true on success, false on timeout
|
||||
*/
|
||||
static bool qspi_cinstr(uint8_t opcode, uint8_t len, uint32_t *dat0)
|
||||
{
|
||||
NRF_QSPI->CINSTRDAT0 = 0;
|
||||
NRF_QSPI->EVENTS_READY = 0;
|
||||
NRF_QSPI->CINSTRCONF = ((uint32_t)opcode) |
|
||||
((uint32_t)len << 8) |
|
||||
(1UL << 12) | /* LIO2: hold IO2 HIGH (not used in single-bit) */
|
||||
(1UL << 13); /* LIO3: hold IO3 HIGH (not used in single-bit) */
|
||||
|
||||
if (!qspi_wait_ready(500)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (dat0) {
|
||||
*dat0 = NRF_QSPI->CINSTRDAT0;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
/* ── Per-config probe and erase ───────────────────────────── */
|
||||
|
||||
static int probe_one(const struct qspi_pin_config *cfg)
|
||||
{
|
||||
uint32_t dat0;
|
||||
uint8_t mfr, type, cap;
|
||||
|
||||
printk(" Probing %s pins...", cfg->name);
|
||||
|
||||
/* Power-enable GPIO if needed */
|
||||
if (cfg->pwr_pin != QPIN_NONE) {
|
||||
gpio_set_output_high(cfg->pwr_pin);
|
||||
k_msleep(2);
|
||||
}
|
||||
|
||||
/* Configure and activate QSPI peripheral */
|
||||
NRF_QSPI->ENABLE = QSPI_ENABLE_ENABLE_Disabled;
|
||||
qspi_disconnect_pins();
|
||||
qspi_set_pins(cfg);
|
||||
|
||||
if (!qspi_activate()) {
|
||||
printk(" activate timeout\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* READ JEDEC ID (0x9F → 3 bytes: manufacturer, type, capacity) */
|
||||
if (!qspi_cinstr(CMD_READ_ID, CINSTR_4B, &dat0)) {
|
||||
printk(" read ID timeout\n");
|
||||
goto fail_deactivate;
|
||||
}
|
||||
|
||||
mfr = (dat0 >> 0) & 0xFF;
|
||||
type = (dat0 >> 8) & 0xFF;
|
||||
cap = (dat0 >> 16) & 0xFF;
|
||||
|
||||
/* Validate — reject bus-float (0xFF) and bus-ground (0x00) */
|
||||
if (mfr == 0xFF || mfr == 0x00) {
|
||||
printk(" no flash (ID=%02X %02X %02X)\n", mfr, type, cap);
|
||||
goto fail_deactivate;
|
||||
}
|
||||
|
||||
printk(" found! JEDEC=%02X %02X %02X (%u KB)\n",
|
||||
mfr, type, cap, (unsigned)((1UL << cap) / 1024));
|
||||
|
||||
/* ── Erase ── */
|
||||
printk(" Erasing QSPI flash...");
|
||||
|
||||
/* WRITE ENABLE */
|
||||
if (!qspi_cinstr(CMD_WRITE_EN, CINSTR_1B, NULL)) {
|
||||
printk(" WREN failed\n");
|
||||
goto fail_deactivate;
|
||||
}
|
||||
|
||||
/* CHIP ERASE */
|
||||
if (!qspi_cinstr(CMD_CHIP_ERASE, CINSTR_1B, NULL)) {
|
||||
printk(" erase cmd failed\n");
|
||||
goto fail_deactivate;
|
||||
}
|
||||
|
||||
/* Poll status register until WIP clears (chip erase: up to 60s typical) */
|
||||
int elapsed_ms = 0;
|
||||
const int poll_interval_ms = 500;
|
||||
const int timeout_ms = 120000;
|
||||
|
||||
while (elapsed_ms < timeout_ms) {
|
||||
k_msleep(poll_interval_ms);
|
||||
elapsed_ms += poll_interval_ms;
|
||||
|
||||
if (!qspi_cinstr(CMD_READ_STATUS, CINSTR_2B, &dat0)) {
|
||||
printk(" status poll failed\n");
|
||||
goto fail_deactivate;
|
||||
}
|
||||
|
||||
if (!(dat0 & STATUS_WIP)) {
|
||||
printk(" OK (%d.%ds)\n",
|
||||
elapsed_ms / 1000,
|
||||
(elapsed_ms % 1000) / 100);
|
||||
qspi_deactivate();
|
||||
if (cfg->pwr_pin != QPIN_NONE) {
|
||||
gpio_release(cfg->pwr_pin);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
printk(" TIMEOUT (>120s)\n");
|
||||
|
||||
fail_deactivate:
|
||||
qspi_deactivate();
|
||||
fail:
|
||||
if (cfg->pwr_pin != QPIN_NONE) {
|
||||
gpio_release(cfg->pwr_pin);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* ── Public API ───────────────────────────────────────────── */
|
||||
|
||||
int qspi_probe_and_erase(void)
|
||||
{
|
||||
printk(" QSPI: probing %d known pin configurations...\n",
|
||||
(int)ARRAY_SIZE(known_boards));
|
||||
|
||||
for (int i = 0; i < (int)ARRAY_SIZE(known_boards); i++) {
|
||||
if (probe_one(&known_boards[i]) == 0) {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
printk(" QSPI: no external flash found — skipped\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
#else /* !CONFIG_SOC_NRF52840 */
|
||||
|
||||
int qspi_probe_and_erase(void)
|
||||
{
|
||||
printk(" QSPI: not supported on this platform\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SOC_NRF52840 */
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Universal QSPI flash probe and erase — bare-metal nRF52840 QSPI register access
|
||||
*
|
||||
* Probes all known pin configurations to detect external QSPI flash,
|
||||
* then performs a full chip erase if found. No Zephyr QSPI driver needed.
|
||||
*/
|
||||
|
||||
#ifndef QSPI_PROBE_H
|
||||
#define QSPI_PROBE_H
|
||||
|
||||
/**
|
||||
* Probe all known QSPI pin configurations for connected flash.
|
||||
* If found, erase the entire chip.
|
||||
*
|
||||
* @return 0 if a chip was found and erased, -1 if no chip found or not supported
|
||||
*/
|
||||
int qspi_probe_and_erase(void);
|
||||
|
||||
#endif /* QSPI_PROBE_H */
|
||||
Reference in New Issue
Block a user