FPGA: requirements.txt & run.ys translate & license headers

fpga/pm5/fpga_pm5_top.v

@@ -1,3 +1,20 @@
+//-----------------------------------------------------------------------------
+// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// See LICENSE.txt for the text of the license.
+//-----------------------------------------------------------------------------
+
+
 module fpga_top (
     input ck_1356meg,
     input ck_1356meg_b,        // B is for close range wiring

fpga/pm5/gowin_rpll.v

@@ -1,11 +1,18 @@
-//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
-//All rights reserved.
-//File Title: IP file
-//Tool Version: V1.9.9 (64-bit)
-//Part Number: GW1N-UV4QN48C6/I5
-//Device: GW1N-4
-//Device Version: D
-//Created Time: Mon Jul  6 18:07:08 2026
+//-----------------------------------------------------------------------------
+// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// See LICENSE.txt for the text of the license.
+//-----------------------------------------------------------------------------
 
 module Gowin_rPLL (clkout, clkin);
 

fpga/pm5/run.ys

@@ -1,11 +1,11 @@
-# 手动综合脚本，等价于 proxmark5_fpga.mk 自动生成的步骤。
-# 在 fpga 目录下运行：yosys -s pm5/run.ys   （构建时请用 make pm5）
+# Manual synthesis script, equivalent to the steps automatically generated by proxmark5_fpga.mk.
+# Run in the fpga directory: yosys -s pm5/run.ys   (use make pm5 for building)
 
-# 1. 读取源代码和宏定义
+# 1. Read source code and macro definitions
 read_verilog -D PM5 -D WITH_TIMODE -D WITH_HF_15 -D WITH_FELICA_PROBE common/define.v common/mux8.v common/clk_divider.v common/lp20khz_1MSa_iir_filter.v common/min_max_tracker.v common/hi_flite.v common/hi_get_trace.v common/hi_iso14443a.v common/hi_reader.v common/hi_simulate.v common/hi_sniffer.v common/lf_edge_detect.v common/lo_adc.v common/lo_edge_detect.v common/lo_passthru.v common/lo_read.v pm5/gowin_rpll.v pm5/fpga_pm5_hf.v pm5/fpga_pm5_lf.v pm5/fpga_pm5_top.v
 
-# 2. 检查并强制指定顶层
+# 2. Check and explicitly specify the top level
 hierarchy -top fpga_top
 
-# 3. 进行综合
+# 3. Perform synthesis
 synth_gowin -nolutram -json output.json

fpga/requirements.txt

@@ -0,0 +1,13 @@
+# Python packages the fpga/ scripts import.
+#
+# fs2bin.py is the only one the build needs, and it normally runs under the
+# python bundled in oss-cad-suite, which already ships apycula - so this file
+# matters when building with an external interpreter instead. apycula owns the
+# .fs bitstream format and its CRC; gowin_devid.py re-derives one of those CRCs
+# and fails loudly if the format ever changes, so bump deliberately.
+apycula>=0.34
+
+# tests/plot_edgedetect.py, the offline plot helper for the edge detect
+# testbenches. Not needed to build an image.
+numpy
+matplotlib